Many papers and articles are claiming that a majority of the defects detected after reflow are coming from the solder paste application process. However,very little real data seems to be available to support this claim. To investigate the paste process impact on defects after reflow,Nokia in Finland and Agilent Technologies decided to do a joint study. The study was designed to use a paste inspection system to measure paste volume directly after the paste application process and to use an automated X-ray inspection system to measure defects after reflow. The first part of the study was to correlate the paste and the X-ray systems to each other using a small number of PCAs. After this correlation study,one week of production volume was analyzed and more than 680,000 solder paste bricks and later solder joints were measured. In this sample,46 defects were detected and confirmed after reflow but,very surprisingly,none of those was detected by the paste inspection. Also very surprisingly,over 2,000 paste bricks had below 65% of nominal paste volume,which in normal production would have triggered a repair action,but none of these -- over 2,000 “defects” at paste inspection -- created a “defect” after reflow.

The control of moisture-sensitive devices (MSDs) prior to SMT reflow is a critical assembly issue that has a direct impact on final product reliability and customer satisfaction as well as manufacturing costs. The guidelines for storage and handling of MSDs are clearly defined in the IPC/JEDEC standard J-STD-033. However,the proper identification,tracking and calculations have always been very challenging to implement with manual procedures and they are prone to a high level of human errors. In most cases,implementation of an internal manual control procedure requires simplifications to the industry standard. This can have two possible effects:
1. When simplifying on the safe side,the user will end up baking parts that don’t really need it. This has serious implications in terms of lead solderability and solder joint reliability due to intermetallic growth. It also impacts material availability,which can affect production schedule,on-time delivery and inventory levels.
2. With other simplifications to the standard,a significant number of components that should have been baked will be assembled and reflowed. Although this may only happen to a small percentage of all the lots,it will typically involve a partial tray or reel containing many parts. Since MSDs are typically the most expensive components and there can be many such components on each PCB,even a small level of escape (less than 0.1% by component) can result in very high material costs and unacceptable levels of early life failures. It is now possible to use an automated control system that is both simple-to-use and can insure a very high level of control. The foremost objective of the system is to avoid assembling components that have exceeded their allowable limit. This is achieved by automatically tracking each reel or stack of trays from the time they are removed from their original dry bag until all parts are placed prior to reflow. The second objective is to minimize the number and duration of bake cycles by taking into account all applicable rules from the industry standard and ambient conditions,while providing real-time status and advance warnings.

As 0402 has become a common package for printed circuit board (PCB) assembly,research and development on mounting 0201 components is emerging as an important topic in the field of surface mount technology for PWB miniaturization. In this study,a test vehicle for 0201 packages was designed to investigate board design and assembly issues. Design of Experiment (DOE) was utilized,using the test vehicle,to explore the influence of key parameters in pad design,printing,pick-and-place,and reflow on the assembly process. These key parameters include printing parameters,mounting height or placement pressure,reflow ramping rate,soak time and peak temperature. The pad designs consist of rectangular pad shape,round pad shape and home-based pad shape. For each pad design,several different aperture openings on the stencil were included. The performance parameters from this experiment include solder paste height,solder paste volume and the number of post-reflow defects. By analyzing the DOE results,optimized pad designs and assembly process parameters were determined.

Like many other phrases carelessly thrown around by economists and business consultants,Return on Investment has become the overused acronym ROI,and has gained popularity so quickly that engineers more accustomed to dealing with SMT,VOC,PTH and ICT now use ROI as part of their everyday working language. But do those of us who use the acronym actually know what ROI really measures or captures in the manufacturing arena? Do we understand how can it be used to both justify and quantify investments in capital equipment? In fact,is ROI even an appropriate data point given the available manufacturing information flows?

Eutectic Bi-42Sn solder is a low melting point alternative to lead-based solders,particularly for low cost,consumer electronics. In earlier work,the mechanical properties of this solder have been enhanced by small additions of silver (0.5%-3%). In this study,Bi-42Sn-1Ag solder paste was used to assemble lead-free PBGAs (Sn-0.7Cu,Sn-3.5Ag,and Sn-3.5Ag-0.7Cu ball compositions) on lead-free PCB surfaces (organic solderability preservative (OSP),electroless nickel/immersion gold,and immersion tin). These lead-free assemblies exhibit accelerated thermal cycling (ATC) performance comparable to the performance of assemblies made with Sn-37Pb,surviving 7000 cycles (40 min. cycles between –25?C and 75?C). In addition,with sufficient solder paste these lead-free assemblies have bend strengths approximately equal to the strength of a comparable Sn-37Pb assembly. Moreover,bend failure occurs between the FR-4 and the inlaid copper pad for both solders. To understand the reliability and mechanical behavior,cross-sections of solder joints were evaluated.

This paper will discuss the implementation of real-time automated SPC for the Reflow Process. Topics covered will include: a new statistical method for quantifying the thermal process performance; methods for ensuring that SPC data provides a true representation of process capability; and the value of automated real-time SPC. To realize the full benefit of an SPC program,it is essential to define and set process specific control limits. SPC programs based on “targets” rather than process specific control limits are not capable of reliably predicting process trends,which is the primary function of an SPC program. Developing a fully functional SPC program requires a sufficient data set on which to project process trends. Another key factor in the success of an SPC program is efficiency. An inefficient method of data gathering and analysis is a guarantee of failure,as a program that consumes excess resources will quickly be abandoned. One method for increasing SPC program efficiency is to focus on key process statistics. A statistical method has been developed that reduces all key process statistics to a single number: the Process Window Index. The calculation of the process Window Index will be defined and its validity as a statistical method for developing Cp and Cpk for the reflow process established. The continuous and automated gathering of data is essential for successful SPC monitoring of the reflow process. Current methods generally rely on periodic profiling,which disrupts production and provides an inaccurate “picture” of the process. Automated Continuous Monitoring Systems for the reflow process have been developed. These systems can provide a data point for every board processed by calculating a “Virtual Profile”. A design of experiment (DOE) will be run to establish that the “Virtual Profile” is a reliable method of continuously gathering data on the reflow process. Experiment methods and results will be included. Automated SPC for the reflow process offers significant benefits for Electronics Assemblers. Automated SPC provides a significant sales tool for EMS’s,as it allows them to prove to customers that their reflow process is in control and that their facility is dedicated to quality electronics assembly. This paper will be of interest to engineers and managers interested in increasing reflow process efficiency and quality.

Wafer-applied underfills are key to the widespread acceptance of flip chip technology. This NIST-ATP funded consortium is developing the materials and processes for achieving a wafer-applied underfill system that is both self-fluxing and reworkable. In the present work,the factors impacting successful assembly of pre-underfilled chips are studied. Flip chips with the underfill material pre-applied to the devices were assembled in the lab using production equipment. The presence of the underfill coating was examined for its influence on vision recognition,placement and reflow.

Flip Chip on Board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases,assembly processes are not capable of providing the high throughputs needed for integrated Surface Mount Technology (SMT) processing.1 A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface.2 This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages,reflow profile parameter effects on eutectic solder wetting of high lead solder bumps,interactions between the no-flow underfill materials and the package solder interconnect and tented via features,void capture and void formation during processing,and material set compatibility and the effects on long term reliability performance.

Automated Optical Inspection (AOI) equipment has become an option for electronics manufacturers who are considering how to improve performance on the production line. During the last few years rapid changes have occurred in mounting technology for PCB assemblies. At the same time that equipment has changed in order to be able to build to the new market requirements,new techniques are needed to test/inspect those new products.

The latest types of components launched by the leading component manufacturers have increased the need for process control in rework. These packages are referred to by the generic name Land Grid Array (LGA) or the specific package names Leadless Leadframe Package (LLP) and Micro Lead Frame (MLF). These packages are unique because they contain multiple pad sizes and shapes on the same device. They are also soldered with all terminations on the underside of the package,similar to BGA. These components lend themselves to normal assembly techniques such as screen-printing the PCB,automatic pick and place,then convection reflow. The LLP design has a large center pad that is often soldered to PCB as a ground or power connection. The soldered center pads can also act as a heat spreader to the PCB substrate. This helps keep the part cool and controls expansion of the part to the substrate so that the TCE (Thermal coefficients of expansion) tolerances of the part to the PCB board material are minimized. The rework process for LLPs requires all the pads to be soldered to the same height or the potential for small land connections could be an issue. The solder paste volume used for the center and array pads must be controlled to achieve good,reliable joints.