The ideal outer layer has a uniform circuit height throughout the board. This is a challenge to produce with pattern
plating,because the plated metal height depends on the current density,which varies across the board,based on the
size and proximity of features being plated. The resulting board typically has areas where the plating height is higher
than desired (overplated),and can be particularly acute in areas of fine lines and spaces. In these areas,if the plating
overlaps the top of the resist,then the resist is difficult to strip cleanly,and this can be the limiting factor in whether
a fine line board can be made in production.
Clean stripping from overplated lines is an area of active research in our laboratories,and we would like to report
the factors in resist design and processing that affect it,and recommendations for driving to finer lines and spaces in
production.

The demand for small packaging for portable electronic equipment and reduced chip form factor with higher interconnect fan-out,is driving printed circuit substrate technology rapidly forward. The demand is for smaller,thinner,lighter,more reliable and,of course,cheaper devices. Just consider the paradigm provided by the cellular phone,the laptop or the PDA in less than a decade. At the interconnect level this means ultra thin high layer count PCBs,densely populated on both sides,maximizing surface mount 'real-estate' and that requires high density interconnectivity. Reducing PCB line and space widths is certainly a proven method for increasing circuit density,but further reductions will demand significant process control improvements to prevent yield losses from driving production costs up. Enhanced interconnectivity is a second important driver. Today's 'state-of-the-art' boards call for a rapid growth in this. This demand,for escalated pad density,is being met by a variety of techniques with every increasing hard to remember acronyms,most of which require high density interconnect structures. A better target for major leaps in connectivity improvement comes from a reduction in the size of via holes and their associated lands,which per se immediately creates more routing tracks between pads. The HDI PCB in 1997 averaged ~ 485 I/O's per square inch,in 2001 it was closer to 1,800. As device form factors shrink and I/O density mushrooms,the size of vias must fall and their number increase. Expressed in another way,the typical '97 PCB via count of 20,000 has increased by more than a magnitude to closer to 250,000. Currently there are several entry routes for the manufacture of PCBs with laser drilled micro via interconnect features:
1 "Half-Etch" route
2 "Conformal Mask" route
3 Thin Foils + Oxide Conversion route
We will describe the key features and disadvantages of each of the current production techniques.

The development of digital printing systems for printed circuit board legends (a.k.a. nomenclature,indent or letter
screening) is a major technological leap. Legend marking on printed circuit boards (PCB) is presently being
accomplished with screen-printing. This method of marking legends on PCB’s provides a permanent,high contrast
mark,however,this technology is costly in terms of material and labor. Screen-printing is a mature technology that
is well understood in the industry and well supported by screen ink providers. A successful digital printing solution
for this application will retain the benefits of permanent,high contrast marks and offer advantages of demand
printing including efficient runs of small production batches.
An emerging technology in PCB legend marking is drop-on-demand (DOD) ink jet. DOD ink jet offers the
flexibility of digital printing while also providing high contrast,high resolution marks with the required performance
properties. The primary advantage of DOD ink jet printing enables PCB’s to be printed directly from image files
eliminating the need for screens and greatly reducing the setup time required between batches. As the PCB industry
is challenged to reduce costs and improve turnaround times,drop-on-demand ink jet shows promise in reshaping the
printing process.

This paper presents a comparison of several resin systems on different support reinforcements including on
Thermount®1 (or NWA),E-Glass (or E),and NE-Glass2 (SITM) (or NE). The resin systems compared in this paper
include D53001 (Halogen-Free,High Tg or HFHT),N4000-13 (high-speed/low-loss or HSLL),and N4000-6 (high
Tg FR4 or HTFR). It is proposed that the HFHT resin can be used for high-signal speed applications,chip-test
boards,and in some cases,lead-free solder PCB processes. The parameters compared herein include thermal,
mechanical,dielectric (i.e.,stripline tests),flame -retardant character,and cure profile characteristics. This study
gives the chip-test board,backplane,and wireless base-station designer valuable information concerning the
functionality of these resin systems with different support reinforcements.

The physical placement of embedded singulated capacitors in relation to one another and to other board structures could have an impact on the measured capacitance of individual capacitors. For board designs requiring tight tolerance of an embedded singulated capacitor,knowledge of the influence of board design on the measured capacitance would be of interest. A designed experiment tested the effect of 3 factors: distance between capacitors (capacitator spacing),the presence of an additional ground plane in the board,and having a common ground for the adjacent capacitors. Test design,board construction,and resulting capacitance measurement data will be presented. The results showed that all 3 main factors and 1 interaction term were significant. The significant interaction was between capacitor spacing and common ground.

Typically thermal cycle test requirements for printed wiring boards (PWBs) are somewhat arbitrarily established for
a particular product. Many programs simply default to a standard test without much quantitative analysis. With
product reliability and cost management pressures,developing realistic accelerated test criteria is vital. The
procedure described in this paper is based on substantial measured field environment data,a validated acceleration
model with a generalized product definition,and statistically based test requirements. While the particular example
is for commercial air transport avionics,the proposed procedure is easily extensible to other high reliability
applications.

Utilizing continuous lamination techniques,new materials are being developed to meet demanding market
requirements. Laminates produced using Thermosetting Polymer Alloys (TPA) are cost effective products that
can be employed in RF and microwave applications. A family of unique products has been developed that
provide various solutions for microwave applications with electrical,mechanical,thermal and processing
characteristics that surpasses competitive products.
Today's high-speed electronic products also require cost-effective materials to enable timely market penetration
and sustained growth through subsequent cost reductions. The technical demands for these products have seen
operating frequency increase or data transmission rates increase to a point that high performance circuit laminate
must be employed to create reliable performance for the consumer. Until very recently,those applications
requiring high performance laminate materials had few options. Even with some of these existing material
options,laminate premium could be as high as 3-10 times and fabrication techniques required could multiply the
costs even further.

Direct Current plating in acid copper baths containing organic supplements shows us that during electrolysis,these organic additives are attracted by the copper anode and being adsorbed on its surface. If this organic layer on the copper's surface is thick enough,it has a restraining influence on the conductivity of this electrode. The anode is becoming passive or the anode is polarized. In no small measure,polarization is dependent on the (anodic-) current density. Using the appropriate additives for the copper electrolyte and applying the right (anodic- )current density,polarization can be controlled and thus improving surface distribution of the electroplating deposition on a Printed Circuit Board.

The design rule of PWBs and substrates for plastic packages is moving towards higher density as semiconductor
chip design evolves into increasingly finer lines. First,it was studied how fine the conventional subtractive process
could build line and found that line/space of that process is limited to around 40/40,even if using some new
technologies. The next challenge was to find a process that can build line/space and get rid of some issues of the
additive or semi additive process. It was confirmed that the improved pattern plating process used with CSE
(Controlled Surface Etching) process is capable of making finer line/space circuits like around 25/25 microns. The
CSE process is characterized by a uniform etching of the base copper with an improved soft etching solution.

As the trend to increased interconnection density continues,conductive printed circuit board features become closer and closer together. It is now common to see 3 mil lines and spaces on local areas of circuit boards,and via spacing of less than 10 mils. As the feature spacing gets smaller the probability for Conductive Anodic Filament (CAF) growth becomes significant. Many PWB designs now require the use of CAF resistant substrates to reduce the opportunity for CAF failures. Early solutions to CAF required use of Non FR-4 substrates such as Bismaleimide Triazine based materials. To meet the increasing requirements for CAF resistance and use the current PWB fabrication process,new FR-4 materials are needed. CAF is the growth of a subsurface filament from an anode to cathode. This is the result of an electrochemical corrosion process that causes deposits of corrosion byproducts along the fiberglass filaments to form. The current model of CAF formation and growth involves two steps,the physical degradation of the fiber/epoxy bond followed by an electrochemical reaction responsible for conductive deposits to form. There are many factors that can contribute to CAF formation. These are summarized in Figure 1. Efforts to develop FR-4 substrates more resistant to CAF growth have focused on both improving the Epoxy -Filament bond and reducing the probability of the electro-chemical reaction occurring by modifying the FR-4 resin chemistry and the nature of the silane finish on the fiberglass reinforcement. New more CAF resistant FR-4 products have been developed and are now available. The development of these imp roved FR-4 substrates demonstrates that epoxy based FR4 materials can be capable of meeting the requirements for CAF resistant high-density PWB designs. CAF test data comparing traditional FR-4 materials to new FR-4 products developed by Polyclad Laminates will be presented. These new materials have been shown to greatly improve CAF resistance.