The adoption of three-dimensional System-in-Package (3D-SiP) is progressing rapidly,driven primarily my mobile electronic
applications such as mobile phones,PDAs,digital still cameras,and digital video recorders. The underlying,enabling Chip
Size Packaging (CSP) technologies can be broadly classified into two types: chip-stacking and package-stacking. In Japan,
both of these stacking methods have reached maturation in terms of the fundamental manufacturing processes required for
cost-effective mass production. Meanwhile,chaos reigns on issues such as supply logistics and IP ownership.
This paper and presentation will focus on the examples of increasingly high-function mobile electronics applications enabled
by 3D-SiP being developed and released into Japanese and overseas markets,as well as the accompanying demand for
continued 3D-SiP technology development based upon industry-wide standards in order to encourage and support rapid
adoption in the marketplace.

Buried Capacitance1 (BC) laminates products have been in use in many high-speed applications for more than ten
years. BC products are a significant contributor to complex multi-layer printed circuit board construction and also a
major element in power distribution circuit design. The principle features of thin laminate BC technology are high
frequency by-pass decoupling capacitance,very low loop inductance and EMI shielding. The newly developed,less
than 2 mil thick,BC laminates shall allowed circuit designers to make significant advances in electronic systems
speed,performance and reduce overall product cost. Manufacturability and reliability of the advanced.

Electronic devices with high performance are becoming smaller and lighter. The passive components required to
enable high performance consume premium space on the surface of the printed circuit board. Integrating the resistor
function into the laminate substrate frees up the PCB surface area consumed by the discrete component,enabling
increased device functionality by the placement of more active components. When the typical 5 to 20 % tolerance of
embedded resistors can be allowed,the resistors satisfy the device requirements. The resistive materials and the PCB
fabrication processes used to fabricate the resistors are currently not able to achieve precision of 1 % or less.
Laser trim technology achieves < 1 % tolerance on thin film embedded resistor panels. The resistive material has an
effect on the efficacy the laser trim. Thin resistive films are laser trimmed to a high degree of precision. Thin film
alloys of nickel and chromium,due to the good thermal stability of the alloy,are trimmed to high accuracy at high
speed.
The printed circuit board manufacturing processes may induce a shift in the resistor value as well as widen the
tolerance. Environmental stress during use may also widen the tolerance. The resistance value and tolerance of laser
trimmed thin film nickel-chromium alloy selective etched embedded resistors was measured after PCB process steps,
and after environmental stress tests. Thin film embedded resistor tolerance is quantified after multilayer lamination,
humidity exposure,convection reflow,solder heat,and thermal cycles.

Lower cost is frequently listed as the main driver for moving to embedded passives. Unfortunately,understanding
the true cost difference between a design using embedded passives and the same design using discrete passives is
complicated. These discrepancies span design,board fabrication,materials,and assembly. While a variety of factors
influence the cost difference,one of the major cost drivers involves layer count and board size. Designs with
embedded passives often fit on smaller boards when compared to designs with discrete passives. However,although
the cost per square inch of the embedded passives board is higher than the discrete alternative,the total cost of the
smaller board may be less.
This paper analyzes drivers that influence the design size and layer count. A methodology is presented for
accurately predicting the final size and cost of designs with embedded passives as well as with discrete passives.
This methodology includes design routing analysis,escape routing analysis for BGA’s,board surface area analysis,
and panelization details. The cost impact of these size differences is also analyzed using activity based cost models
for board fabrication and assembly.

This paper presents an emerging technology for embedding discrete ceramic thick-film capacitors directly into
printed circuit boards. Their use frees up surface real estate allowing for smaller boards and/or for more silicon on
the board. They also lower inductance,impedance and radiated emissions. Previously,the technology has been
limited due to lack of component values,performance and availability of commercial materials. These issues,
however,are being eliminated and CTF embedded passives are emerging as a feasible technology. The CTF
capacitor materials are robust,and discrete capacitors can be designed to a wide range of values and physical shapes.
Materials,processes and design guidelines and manufacturing tolerances are discussed. Drivers are performance,
miniaturization,and cost.

Successive generations of ICs demand higher peak current levels and faster current rise times,challenging traditional surface
mount decoupling. The considerably lower parasitic inductance of integrated capacitors and the structures associated with
them are an enabling technology to prevent decoupling from becoming a system limitation. In addition to better electrical
performance,integrated capacitors eliminate the solder joints that must be placed at the hottest part of the board,improving a
significant reliability issue,and free up real estate near the chip for other uses.

Embedded passives are entering a new phase of improved product capability and enhanced processes. Thinner,
higher capacitance embedded distributed capacitance (EDC) materials are coming to market. Alternate resistor
forming and trimming technologies have recently been released,and discrete embedded capacitor technology is
emerging. This paper will focus on embedded distributed capacitance and embedded resistor technology,with a
brief discussion on embedded discrete capacitors and supporting technology.

This paper will highlight the shortcomings of each of the commonly used surface finishes available on the market
today. The goal is to spark the industry interest,that it may double its efforts in resolving the technical issues
surrounding the existing processes and to develop emerging products.
This discussion will be from the OEM’s point of view,as well as concerns from the Fab and Assembly side of the
equation. Finally,the paper will also discuss the industry needs going forward; especially regarding the tight pitch
tendencies and higher speed requirements of future systems.

The development of two new industry specifications – IPC-4553 (immersion silver IAg) and IPC-4554 (immersion tin ISn)
are well under way. Following in a tradition started with the development of the 4552 ENIG specification,it is customary for
this committee to present an update in the form of a technical paper on the progress of any specification under development.
The acceptance and subsequent release of any technical specification should be based on the data generated to justify it. This
committee prides itself on data generation being the backbone for any specification that it works on. This technical report
outlines the data generated to date,for both immersion silver (4553) and immersion tin (4554) deposits. Some of the data is
from completed tests while other data sets are ongoing.
As with the 4552 ENIG specification it is the intention of this committee to justify all parts of these two specifications
currently in progress with a completed technical paper that will be attached to the document in the form of an appendix.

Sn/Cu lead-free solder is a good alternative to 63/37 solder for use in HASL processes. Solderability of Sn/Cu
surface exceeds that of 63/37 solder,nickel-gold,OSP,silver,and immersion tin both before and after heat induced
aging.