This paper addresses the growing need in the Printed Wiring Board industry to measure and test propagation delay
parameters of board interconnects within the fabrication process. The state of current art is detailed in discussions of four
different methods of measurement including their respective advantages and disadvantages. Definitions and basic
considerations for the measurement process are also discussed. The conclusion is that accurate and repeatable measurements
of propagation delay in the manufacturing environment can be made with existing equipment technology and with a best
known method.

Designing a signal path to provide a particular impedance is thought to be a well understood science. The first issue which is
often overlooked is to analytically establish the need for specifying a controlled impedance signal path. After determining
this to be the case,the designer normally selects a combination of line width and dielectric thickness to satisfy the stated
requirement. There are usually,however,an infinity of selections that will satisfy any stated impedance requirement.
Obviously,one would prefer to select the combination that will minimize variations in the impedance caused by the
fabrication process. This becomes extremely important in designs using low impedance paths such as Rambus.
This paper discusses an analytical procedure addressing these issues. Once the optimal selection is made,it is then possible as
further described in this paper,to define the statistical variation of the impedance to be expected for the optimal construction.

Abstract
Electroplated tin and tin alloy coatings are used in electronics plating applications as a solderable and corrosion resistant
surface finish for components and printed circuit boards (PCBs). Though applications vary,there are some commonalities
regarding the requirements for this final surface coating. One issue is long term solderability performance,defined as the
ability of the surface finish to wet with solder and form a reliable solder joint to the next-level substrate without defects
that would impair the electrical or mechanical interconnection.
There are many factors that determine solderability performance of an electroplated coating,surface oxide formation being
foremost among them. The rate of formation of the surface oxide depends on the temperature and time of the thermal
excursion the component or PCB is exposed to - the higher the temperature and longer the time,the thicker the surface
oxide that is formed. To ensure the highest degree of solderability,it is important to prevent or minimize exposure of the
tin plated surface to elevated temperatures for extended periods of time.
In terms of production implementation,this is often very difficult to achieve because the type and duration of thermal
excursions is dictated by post-plating processing conditions and/or end-user specifications. For example,in the case of Pbfree
component pure tin plating,many end-users have begun to specify that a “stress relief bake” (SRB) of typically 150°C
for one hour be implemented to reduce compressive stresses in the deposit to minimize long term whisker growth
propensity of the deposit. After the SRB,the component still has to pass end-user solderability testing requirements which
typically involve additional heat and humidity conditioning. Inevitably,this causes thicker surface oxides to form,which
in turn reduces the solderability performance of the tin or tin alloy deposit and indeed today in current semiconductor Pbfree
component processing,it is very difficult to pass the most stringent end-user solderability test requirements after
implementation of the newly required SRB. Therefore it would be highly desirable to find a way to prevent or minimize
surface oxide formation on such deposits.
This paper will introduce a new patent-pending technology which minimizes oxidation of tin and tin alloy coatings
through implementation of a proprietary additive in the electroplating bath. Results in terms of demonstrating reduction of
surface oxide formation resulting from this technology as well as improvements in solderability performance from both
laboratory studies and production will be presented.

For decades,tin-lead has been used as the primary surface finish for compliant pins and plated through holes (PTH) of
printed circuit board (PCB) in press-fit connections. Therefore,most test results on press-fit performance are focused on the
tin-lead finishes for the connections. Due to the discontinuation of the use of lead in electric and electronic components,the
trend of using lead-free manufacturing for PCB’s and connectors is being vigorously pursued by the industry. The present
study is intended to evaluate press-fit connections using various lead-free finishes on compliant pins and PTH’s and then
compare to tin-lead finish. The lead-free finishes for the compliant pins are plated with matte and bright pure tin,and the
lead-free finishes for the PTH’s are electroplated Au,OSP,and immersion tin,Au,and Ag finishes.
In the design of experiments (DOE) of the current study,single pin tests were used to obtain the DOE outputs of insertion
and retention forces for eye-of-the-needle (EON) compliant pins in PTH’s. For all three EON finishes (two pure tin and one
tin-lead),the DOE results show that finished PTH size is the most important factor to determine the insertion force. The
insertion force is a strong inverted linear function of finished PTH size (i.e.,a larger force is required for a smaller finished
PTH size). The impact from pin installation/repair cycle is the second factor behind the finished PTH size. The finishes of
EON and PTH are only minor factors for the insertion force. In contrast to the insertion force,the retention force is rather flat
regarding the finished PTH size. The DOE results also indicate the EON finish is ranked as the number one factor to affect
the retention force. The matte tin EON pin produces higher retention force than the tin-lead finish. The EON of bright tin
finish produces a slightly lower retention force than the tin-lead. Within the five lead-free and one tin-lead finishes for the
PTH’s in the study,the lead-free finishes of OSP,immersion Au and electroplated Au provide retention forces in the lower
end,and the immersion tin always provides the highest retention force. However,each of these combinations results in stable
electrical performance and a reliable connection.

As an EMS provider of high complexity backpanel assemblies,traceability of components with performance issues found at
system test,functional test and in the field was limited to the ability to trace the raw board or fab defects and not much more.
As more and more technology was being integrated into these complex backpanel assemblies,customers began in earnest to
require EMS providers to provide traceability of components as well as fabs. Endicott Interconnect Technologies attempted
to track a few critical components,such as ASIC modules and power supplies manually. This quickly became unmanageable
logistically and the manual process of logging data in notebooks was unreliable. It was apparent that an automated system
needed to be developed,that could integrate with automated manufacturing equipment,in particular the pick and place
equipment. Utilizing the central processor and employing the on board software and some available industry software,data
generated during component placement would be used to develop the component traceability database. Modifications to all
portions of hard and soft tools would have to be made to integrate them into our server database so we could offer a reliable,
dependable and economic solution to this problem. This paper will describe the solution that was developed to solve this
challenging problem.

Fabricators,and the copper plating process they choose,can have considerable influence on their customers' solder joint
reliability. In the case of high density assemblies,via-in-pad designs often cause solder joint void formation due to the
trapping of air and/or other contaminants. If large enough,these voids can compromise reliability in the end systems they
inhabit. This paper helps the board fabricator and the contract assembler understand how the copper plating process affects
voiding levels in solder joints,for via-in-pad Printed Circuit Boards (PCBs). We compare three different plating methods for
filling microvias,and then study the impact of these methods on the occurrence frequency and size of these voids. Three
types of plating processes were analyzed: conformal plate (no via-fill),a one-step via-fill,and a two-step via-fill. Voiding
frequency and size were determined from sample cross-sections and X-ray inspection. It is observed that even "low success"
in filling the vias can significantly reduce the void size and occurrence in the solder joints.

In the United States,focus turns toward enabling technology for quick-turn printed circuit board and laminate package
manufacturing. The current corporate mandate is to develop advanced,enabling technology,and to integrate it rapidly.
Reduced via diameter,and higher layer count at lower cost for laminate packages and printed circuit boards continue to be
pursued,as they are key elements for higher density products. Filling vias with increased aspect ratios (depth/hole diameter)
had become a poser,and inefficient squeegee print methods were replaced to a great extent by injection methods. Novel via
fill injection and or vacuum applications,along with peripheral devices for post-fill processing enable the manufacturer to fill
higher aspect ratio vias having diameter to depth ratios greater than 10:1,with reduced cycle time.
Hold the phone! Are all the necessary elements in place? As with any new technology,we discover missing pieces as we go,
and new demands are placed on any given process that must be dealt with in turn. As via protection becomes more defined,
hole-fill tolerances are made more stringent and correspondingly,more difficult to measure. How do we now inspect the
product as efficiently as we process it? Other questions emerge. How are higher Tg laminate materials affecting both board
and process? How well do the laminate and via fill materials compare regarding Z expansion? What are materials suppliers
doing to address the disparity of x and y thermal expansion in ppm vs. z expansion in the percentile range.
Studies regarding various paste materials,their behavior,and integration into advanced production applications from the
printed circuit board,to hybrid microelectronics materials and others,have afforded an opportunity to observe and assess
current capabilities,as well as to gain insight into issues that have cropped up in terms of via protection. This paper will (in
common-sense terms),attempt to look at pertinent issues regarding via fill paste and laminate material properties,general
process enhancements,perhaps some novel approaches to inspection of post-via fill panels and repair methods,with a
smattering of selective via process concepts,and paste rheology contribution to that process as well.

Optomec is developing an aerosol-based technology for high-precision,maskless deposition of a wide variety of
materials. The system functions by atomizing commercial inks and pastes,and then depositing the droplets under
CAD/CAM control. Feature sizes of 25 microns and smaller are achieved and millimeter-scale tool standoff allows
non-contact deposition into vias,trenches,and three-dimensional geometries. The compatible materials include a
variety of commercial metals,resistors,dielectrics,and polymers as well as custom specialty materials. The
materials can be laser sintered or thermally cured and are compatible with ceramic and glass substrate as well as
various low-temperature substrates such as epoxy circuit board and flexible polymer film. This technology is called
Maskless Mesoscale Materials Deposition (M3D).

x

A vertically configured package technology developed by Tessera is proving to be a practical multi-die solution for any
number of single and multiple functional combinations. The enabling technology for this stacking approach allows different
sub-structures individually assembled,tested and joined together electrically and mechanically in a secondary process while
still maintaining a small,single die footprint. This combining of several die sizes with varying functions within a single finepitch,
low profile BGA package outline is achieved using thin flexible polyimide substrate as a base and adapting a unique
combination of folding and package stacking methodology. In addition to the folded and stacked combinations,individual die
can be configured for vertical stacking. In the case of memory for example,the single die can be packaged,tested,and
marketed as unique sub-structures,allowing each die type to be sourced separately from multiple silicon vendors. This
“layered” approach to packaging is designed to improve yield,resolve test concerns and overcome the business issues
hindering the wide-scale adoption of multi-die solutions. The paper examines several alternative 3D multiple-die package
solutions that solve many of the multiple die source problems while delivering the expected performance and cost benefits.