Solder voiding is present in the majority solder joints and is generally accepted when the voids are small and the
total void content is minimal. X-ray methods are the predominate method for solder void analysis but this method
can be quite subjective for non grid array components due to the two dimensional aspects of X-ray images and
software limitations. A novel method of making a copper “sandwich” to simulate under lead and under component
environs during reflow has been developed and is discussed in detail. This method has enabled quantitative solder
paste void analysis for lead free and specialty paste development and process refinement. Profile and paste storage
effects on voiding are discussed. Additionally an optimal design and material selection from a solder void standpoint
for a heat spreader on a BCC (Bumpered Chip Carrier) has been developed and is discussed.

A number of prior studies have established that solid state migration of solder alloy elemental phases will occur as a
function of temperature,time and voltage bias through the solder joint. This study undertakes to develop and
evaluate a novel semi-quantitative means of physically characterizing the degree and amount of phase segregation
taking place in reflowed BGA solder joints. This is accomplished through the use of quantitative image analysis of
overall and regional area spatial relationships of cross sectional SEM micrographs of BGA joints. The SEM images
distinguish between the metallurgical phases on the basis of their differing atomic masses. Statistical comparison of
various image regions within a joint subsequent to reflow facilitates computation of an index to assess the degree of
solid state movement within a BGA joint with time.

Although wave soldering has not historically been considered a well-controlled process,its evolution over the past
decade makes it a prime candidate for effective control methods. These methods are not complex,but relatively
simple and inexpensive to implement and maintain. Furthermore,they can be applied to lead-bearing or lead-free
processing.
Wave soldering is a relatively simple process to convert to lead-free,but the conversion brings subtle changes that
result in a tighter process window. This paper outlines the harmful effects of out-of-control process parameters and
describes methods of measuring and tracking them to keep them in control. It identifies and addresses the critical
variables of wave soldering - flux deposition,preheat application,conveyor speed,solder temperature,solder
contact time – and describes the similarities and differences between lead-bearing and lead-free processing.

Currently,PWB industry is striving for the cost down at the daily PWB manufacturing,and at the same time,they are
developing the higher density PWB for the future application.
The emerging 300 kmin-1 spindle will shift the overlapping point from mechanical drilling to Laser drilling for the Through
Hole (T/H) of PWB core material smaller than 100 µm diameter.
The micro via drilling for glass reinforced core material smaller than 75 µm dia. by CO2 Laser machine,and 20 µm dia. by
UV laser for future application are under study. Now I would like to share the stage of development for mechanical and
Laser drilling technology.

Today’s HDI field of technology is coming under more and more pressure to increase wiring density and,even more
importantly,to decrease manufacturing costs. The current technological approach does not permit an adequate response to
this challenge and thus new,disruptive manufacturing technologies have to be developed.
Imprinting as a means of forming conductor patterns as well as via holes has been under discussion for several years now. A
more crucial issue,however,is to find a method for filling the recessed features reliably and inclusion-free with solid copper,
and consequently the overall build-up concept has to be adapted in order to utilize the full potential of this novel technique.
This paper describes a new manufacturing approach based on imprinting,a special copper plating process,followed by an
etch-back step. This method is capable of producing lines and spaces down to 10µm and thicknesses of up to 40µm.
Conductor and via pattern are produced simultaneously,thus making padless designs feasible.
The key elements of this radical new approach are the manufacture of the imprinting stamp,the imprinting itself and the
copper filling. Each necessary process step has been verified in a lab environment,and first functional samples have been
successfully produced. Continuing further development is underway to bring this technology from lab to fab within a
reasonable timeframe.

JPCA has been developing standards necessary for adoption of optoelectronic technology especially for consumer
applications for years. The subjects being drafted are the technology that is fairly matured and actually used in some
applications in the industry. JPCA has identified some seventy items for standardization and published seven
documents as the first set of documents in June 2003. Another dozen documents will be released in the spring of
2004. IPC-0040 has been just published and is an excellent guideline for optoelectronic assembly technology we
need. It is our hope that the documents developed by JPCA will be a part of the documents to be developed based
on the recommendation made in IPC-0040. We expect our effort will encourage people in the industry to
incorporate OE technology in their design of new products,not only in the area of telecommunications but rather in
the areas of consumer applications and information processing including but not limited to computers,game
machines and others.

Reliable copper interconnects are a primary requirement for most printed wiring board applications. A variety of
wet manufacturing processes play an important role in the formation of durable interconnects,including plated thru
hole (PTH) metallization with electroless copper/electrolytic copper plate. PTH interplane (IP) separation may
become an issue when cleanliness and texturing of the IP before electroless deposition is not optimal. Smear
removal pretreatment and subsequent processing to provide a clean and properly textured IP before electroless
deposition have a strong influence on the resulting roughness and chemical content of the outermost layer of copper
surfaces. A method by which to evaluate the surface state of copper during each preclean and chemical processing
step would be beneficial to understanding copper surface chemistry,and consequently,some of the origins of IP
separation.
The tendency for a metal surface such as copper to undergo electrochemical corrosion can provide some qualitative,
as well as limited quantitative information on the relative state of the copper surface after exposure to various
corrosive solutions. For example,copper precleaning solutions,including permanganate desmear and acid
conditioning,are inherently corrosive and are required in order to generate a properly textured clean surface free of
contaminates upon which electroless copper can successfully adhere. The relative corrosivity of the solution the
copper is exposed to during preclean will ultimately affect the corrosion rate or corrosion resistance of the surface
when exposed to yet another corrosive electrolyte. For example,a relatively corrosive preclean step such as sodium
persulfate microetch may leave the copper surface in a more rough,oxidized state than a simple acidified rinse.
Consequently,it could be expected that the corrosion rate of this oxidized copper surface would be relatively low in
comparison to the corrosion rate of a smooth,pure copper surface afforded by a gentler acid rinse. Because IP
separation is a manifestation of poor adhesion between the base copper/ electroless copper or the electroless
copper/electrolytic copper interface,a more detailed investigation of the chemical factors that cause changes in
copper surfaces can be helpful in understanding the underlying cause(s).
With this objective in mind,a copper clad test vehicle was subjected to desmear and electroless copper plate along
with the associated precleans,with a portion of it removed,rinsed and dried after exposure to each individual
chemical processing step. The corrosion behavior of each resulting sample surface was electrochemically studied by
generating Tafel plots of each surface in 0.3% NaCl electrolyte. Corrosion rates of each unique copper surface after
various wet process steps and the corrosion potential of each surface in electrolyte are reported.

Two years ago when IBM Endicott,now Endicott Interconnect (EI),was preparing to install a new Acid Copper
plating system,the Periodic Reverse Pulse (PRP) tanks installed at the end of the line were seen as a current density
capacity enhancement for "standard thickness" boards. At the time,there was limited demand for thicker,higher
aspect ratio boards which required plating in the pulse tanks. A lot has changed in the last two years!
In 2001,electroplated boards with a 15:1 aspect ratio were on EI’s strategic road map; now they are on the
manufacturing floor. The pulse tanks,empty two years ago,have evolved from merely being a productivity
enhancement to becoming technology enablers - plating EI’s highest aspect ratio boards.
This paper will discuss some of the methodologies of the plating system’s design,the strategy deployed in
evaluating and qualifying PRP and the migration to thicker boards. All of EI’s PRP work on the production line has
been done with Atotech's CUPRAPULSE S4 LEVELER system and PE PRP/DC rectifiers,capable of +1200A / -
3600A; but the methodology and results should be applicable for most plating systems. The impact of process
parameters and board features play a major role,but central to our findings is the need to migrate from a "one bath
for all applications" mentality,which compromises results and capability. One simply cannot get optimal results by
merely reducing the current density of their existing bath and just hoping for the best.

The Cray X1™ system dramatically extends the capability of supercomputers with High efficiency and extreme
performance. Specifically designed to meet the needs of the high-end user,the Cray X1 provides exceptional
memory bandwidth,low-latency interconnects and vector-processing capabilities.
While development of the Cray X1 received substantial support from several U.S. government agencies,including
the National Security Agency (NSA),Cray decided to develop its own specifications for printed wiring boards,
materials and reliability.
This paper will discuss the introduction of the Newest Cray X1 Supercomputer,and the requirements of the printed
wiring boards used in the systems. It will also focus on the Unique Challenges of the fabrication of the PWB,the
different materials explored,their properties,and their setbacks. Also addressed will be the stringent electrical test
requirements and the many quality and reliability controls for PCB acceptance from its suppliers.

Design of printed wiring boards allowing devices to function at increasing signal transmission rates is a difficult task. As
operating frequencies increase beyond one Gigahertz the availability and accuracy of Dielectric Constant and Dissipation
Factor data for PWB substrates becomes very limited. To improve the availability of dielectric data on PWB substrates,
Cookson Electronics PWB Materials and Chemistry Sector worked with the Electronics Manufacturing Technology Branch
of NAVSEA to develop reliable test capabilities and evaluate various substrates. The test technique utilized the “Waveguide
Slab” method (1) to measure the Dielectric Constant and Dissipation Factors of various substrate materials between 4 and 18
GHz. Results of the testing of these substrates will be presented. Substrates tested include FR-4,Thermally Stable Epoxy,
Aramid reinforce epoxy,halogen free,Polyimide,BT,and other low DK/low DF materials. Information about the testing
procedure and accuracy will also be discussed.