With design requirements becoming more stringent as implementation of new technology standards evolve,designers are faced with the challenge of front-loading more effort in the design cycle than ever before. The need for simulation in all facets of the product design,whether the Engineer is in the middle of drawing his schematic or a layout designer is in the middle of routing his printed circuit board,has become common.
This introduces a new design task where an Engineer has to hunt for device models or does various what-if analyses to test out the termination scheme or to manage DDR2 functionality within their signal integrity tools. Setting up differential pair drivers and testing them versus multiple layer stack-ups based on a chip maker’s requirements and takes time and effort,and we all know that in most cases,the “time” aspect is relatively scarce. To help in the effort to enhance predictability and turnaround time,a simulation kit can be used as part of the design process.

The routing of large pin-count and dense BGAs has a significant impact on the cost of the PCB,primarily in terms of layer count and via technology. This paper is the result of considerable research done with the intent of providing a general flow solution to the BGA breakout problem. It explores the need for collaboration between chip,package and PCB designers - emphasizing the dependencies that need to be managed to reduce board costs. The number of variables confronted in large BGA routing is significant and this paper reveals solutions based on a logical analysis of ASIC and FPGA BGA pin density,array patterns,packaging requirements,pin swap constraints,layers,via technology,topology planning and routing methods.

The Quad Flat No-Lead or QFN packages are increasing in their utilization in the printed circuit board market. This is being driven largely by the shrinking size both in profile and footprint,higher operating speeds from 2 GHz to 10 GHz,effective thermal dissipation all in a low cost package. The relatively inexpensive nature of leadframe-based CSPs (chip scale packages) such as QFN’s without solder balls has led to the popularity of these devices being utilized in commercial
electronics. TechSearch International reported that there was an increase in the utilization of these devices in subcontractors from 77% to 85% from 2004 to 2005.1 Another example of the increase in utilization,focused in Japan,is that for portable consumer products such as digital video cameras the QFN was found in 5% of applications in 2004 and is predicted to be at 10% in 2014.1,2 Even package vendors such as Amkor Technologies now advertise that they have sold over 1 billion QFN packages.3 As QFN usage grows,they will eventually replace the currently dominate format,fine-pitch gullwing & quad flat IC package,
As with the increase in any type of joint usage,there is an increase in the opportunity for defects. Currently,only generic test requirements for the QFN exist in the industry. Like area array grid packages,the QFN solder joint is below the joint,hidden from most types of optical inspection test. X-ray inspection provides an effective solution in testing these types of joints.

As printed circuit board assembly (PCBA) becomes more complex,Automatic Optical Inspection (AOI) and Automatic Xray Inspection (AXI) systems are becoming more widely used in electronics manufacturing. AXI has good defect detection capabilities,but its TaKT time becomes a concern when compared to other machines (screen printer,pick-and-place,reflow,and wave soldering) on the SMT line. How can these two testing machines be used effectively to test production? This translates into: (1) how can we reduce AXI test time by supplementing it with AOI? And (2) how can we use the AOI and
AXI test results to improve the overall manufacturing process and thereby increase production yields? Some studies were reported in the past with only AXI1-3. We have been doing this project with AOI and AXI test data analysis to improve assembly test yields.
With the Flextronics Manufacturing System (FMS) approach,we focus on Lean Manufacturing. Lean is a manufacturing philosophy that recognizes WASTE as the primary driver of cycle time,and employs techniques to continually drive out
waste in the various processes. Waste elimination is the most effective means to achieve cycle time reduction. We develop new processes to deal with three types of waste: (1) Over process (2) Defect waste,& (3) Inventory accumulation. We used the key elements of Six Sigma DMAIC (Define,Measure,Analyze,Improve,& Control) and statistical tools for the project. In this study we first started with one customer’s product,which previously had 100% components covered with AOI and >95% covered by AXI. We studied AOI,AXI,ICT,and Functional Test data for six months,and reduced AXI test coverage for some non-critical components. As a result of the reduction of AXI coverage,we were able to reduce AXI test time from above 4 minutes to below 3 minutes. In the meantime we also focused on process issues and improvements using daily AOI
and AXI test results. Test and process engineers worked together on this project and used the AOI/AXI test results to adjust the machine settings for solder paste printing,pick and place,and wave soldering machines; solving the process and material issues and making very good progress. An example of one product: We reduced AXI test time by only testing BGA,Fine Pitch ICs,RNs,and some “Critical to Function” parts. Therefore AXI component and pin coverage changed from 98.4%,and 98.9% to 13.6%,50.1% respectively. AXI test time was reduced from 4.1 minutes to 2 minutes. Meanwhile,the yields of AOI (top),AOI (bottom),AXI,ICT,and FT increased from 98.9%,97.3%,88.4%,98.9%,and 100% to 99.6%,99.0%,96.2%,98.9%,and 100% respectively. The cost saving results will be discussed in the paper.

The hidden cost of optical inspection systems is often in the programming time. In this paper we discuss a new AOI programming and inspection paradigm reduces the need for human intervention and improves program stability and quality. This paradigm is based on the principles of adaptability of the human brain. Our understanding of these principles has helped to facilitate the development of easy-to- program automated optical inspection machines that need little human intervention and yet exhibit a consistently high level of performance over extended periods.

An important development in high reliability electronics is the convergence of circuit board and advanced packaging technologies. This combination enhances the best attributes of each technology to achieve higher performing devices. These emerging technologies drive the need for critical cleaning,which requires continued innovation to meet cleanliness requirements. Additionally,the move to Pb-free alloys creates new demands from a cleaning process perspective. To meet
the reliability standards for smaller,lighter,and highly dense electronic assemblies,cleaning process integration between mechanical and chemical driving forces require consideration. Research studies suggest that removal of flux residue from under die packaging technologies reduces voiding and improves reliability. The purpose of this research investigates new
mechanical impingement designs and reports the correlation of Pb-free flux removal efficacy using design of experiment testing.

boards in the in-line aqueous cleaning process. As lead-free circuit boards become more complex and component spacing
decreases,the effectiveness of direct blow-off drying is greatly diminished. Adding blower power or slowing process speed will improve drying performance,but increase operating cost,and may decrease throughput.
This paper describes a new approach to drying circuit board assemblies that significantly reduces the cost of ownership of an aqueous cleaning system. Drying performance is increased through a hybrid drying process that reduces energy input,exhaust requirements and sound levels. The combination of high temperature blow-off and convection brings the flexibility to tailor drying performance to fit the product’s drying requirements

To improve the design efficiency of a micro drill bit,a method on the basis of the combination of theoretical analysis,numerical simulation and experimental verifications is presented. As examples,the theoretical analyses of drill bit stress
and rigidity conditions are investigated with emphasis. To perform such analyses,the finite element analysis (FEA) is recommended. To examine the accuracy of the theoretical analysis result and the performance of designed micro drill bit,
experimental verification is conducted. Two design examples using the presented design method,namely one design of micro drill bit for flexible PCB (FP type) and the other for high Tg PCB (HT type) are discussed.

Society today relies on electronic devices that influence every aspect of our lives,such as communication,transportation,computing,home appliances,and recreation. The reliability of any electronic device depends on the design and quality of the printed circuit board (PCB) assembly. The origin of the PCB begins with a design concept followed by its verification for the desired output. The development of a manufacturing process subsequently occurs with the production of a small volume of prototype PCBs,and scale up to full production takes place once the manufacturing process is established. At each
manufacturing scale up,it is advisable to evaluate and verify the quality of PCBs to appropriate material and/or performance specifications. The first part of this paper describes how we use both types of specifications to perform investigations at first article unpopulated and populated PCBs with the intent of assisting our customer’s selection of a board manufacturing process,and possibly a board manufacturer. A similar methodology is applicable to raw components and geometrical design changes to characterize product process control and/or identify soldering issues. The second part of this paper covers some studies of solder connection reliability,such as Black Pad,and a developing methodology for analysis and control.

The continuous temperature resistance of electrically insulating materials can be judged by examining the effect of thermal stress loads on the electrical properties,such as moisture and insulating resistance,tracking resistance,etc.
Which effects on the electrical insulating properties of solder masks are to be expected,in particular under subsequent climatic stress? This paper will present and discuss the results of moisture and insulating resistance tests in different climates as well as further electrical properties from both continuous storage tests at 150°C for 2,000 hours and thermal cycling tests over 1,000 cycles,-40°C/+150°C. The load at the high cycle temperatures shall be compared with those from the continuous temperature storage tests. Furthermore,the theoretical base of this methodology shall be discussed.
In order to consider any potential "pre-damage" caused by the various surface finishes,tests have also been performed with a "preliminary stress load" comparable to that of the printed circuit board and electronic assembly. The influences of processing with various surface finishes such as Nickel/Gold finish (ENIG),chemical tin finish (CSN) and HAL (Hot-Air Levelling) on the thermal cycling resistance have also been examined. The paper shall go on to discuss investigations into the moisture and insulation resistance in different climates as well as the influence of the base material and layout as well as precleaning and solder mask thickness on the thermal cycling resistance.
In addition,comparisons shall be made between aqueous-alkaline and polyalcohol developable materials.