In response to RoHS and other international environmental legislation,the semiconductor industry is moving toward the
elimination of lead (Pb) from packages. During the transitional period,both leaded and lead-free components coexist with
tin-lead and lead-free soldering processes. The compatibility of lead-free area array packages with tin-lead soldering
processes is a critical issue if the transition becomes prolonged as several product categories may take advantage of the
exemptions and continue to be built with tin-lead solder for some time to come.
The issue of “backward compatibility” arises because for BGA packages,the contribution of solder balls to the solder joint
material is very high (typically of 70% to 80%),and the assembly of lead-free BGA packages with tin-lead paste becomes a
major concern from the perspective of solder joint metallurgical uniformity and reliability.
In this study,the solder joint metallurgy of mixed alloys was characterized,and the amount of mixing of Pb through the
solder joint was analyzed,for different package types and under various process conditions. The results showed that the
solder paste amount (ultimately tin (Sn) percentage in the alloy) and the reflow temperature play critical roles in the mixed
alloy assembly,both in terms of compositional homogeneity and voiding. Homogeneous solder joints were seen at various
reflow temperatures ranging from 210°C to 230°C,depending on the Sn percentage in the mixed solder alloy. This study
will shed some light on the process optimization for backward compatible assemblies in order to improve yield and to create
more reliable solder joints.

The movement to Pb-free soldering will result in solder joints that are significantly stiffer than those made of SnPb. This
paper presents the results from the first phase of a two-part study to understand and compare the isothermal mechanical
fatigue behavior of tin-silver-copper (SnAgCu) solder to that of tin-lead (SnPb) solder. A combination of experiments and
finite element analysis was used to compare and predict the durability of SnPb and SnAgCu surface mount solder joints. The
experiments were composed of cyclic four-point bend tests of printed wiring board coupons populated with 2512 sized
resistors at 5 and 10 Hz. This configuration was chosen so the test would reflect actual electronic products and still be rapidly
modeled using finite element analysis (FEA). This frequency should be sufficiently high to minimize solder creep during the
testing. The board level strains were verified with strain gauges and the solder joint failures were detected using a high-speed
event detector. Tests were conducted at two board level strain values and then modeled in FEA to determine the strains and
stresses developed in the solder joint. This information was then used to determine the appropriate cyclic fatigue relationship
for both SnAgCu and SnPb solder. The results indicate that at high board level strains SnPb solder out performs SnAgCu
solder. However,at lower board level strains the SnAgCu solder out performed SnPb. The second phase of the study involves
bend testing at even lower board level strains to characterize the high cycle fatigue behaviors of the solders.

Chip scale packages (CSPs) are widely used in portable electronic products. Mechanical drop testing is a critical reliability
requirement for these products. With the switch to lead free solder,new reliability data must be generated. Most drop test
reliability data reported for CSPs are for the as-built condition. However,the mechanical shock reliability over the life of the
product is equally important. This work provides a systematic study of surface finish (Immersion Sn and Immersion Ag) and
reflow profile (cool down rate) on the drop test reliability of CSP assemblies. The Sn finish provides an initial Cu-Sn
intermetallic layer,while the Ag finish allows the formation of the initial Cu-Sn intermetallic during the reflow cycle. Drop
test results for assemblies as built and as a function of aging at 125oC are correlated with cross sectional analysis of the solder
joints. The mean number of drops to failure decreases nearly linearly with aging at 125oC through 480 hours. Voids develop
at the Cu-Sn intermetallic-to-Cu interface during high temperature aging,but the crack path is through the intermetallic layer
and does not propagate from void-to-void. Thus,it can be concluded that the voids do not contribute to the decrease in drop
test survivability observed in this study.

In order to meet the growing requirement of eliminating lead from electronics,the printed wiring board (PWB) industry is
migrating from hot-air-leveled solder (Sn/Pb) to lead free compatible alternative final finishes. Among the available
alternatives which include organic solderability preservative (OSP) immersion silver,immersion tin and electroless
nickel/immersion gold,the OSP type coating is considered to be one of the leading candidates because of its excellent
solderability,ease of processing and low cost.
This paper uses Gas Chromatography-Mass Spectroscopy (GC/MS),Thermogravimetric Analysis (TGA),and X-ray
Photoelectron Spectroscopy (XPS) to characterize the relative thermal properties of a novel high temperature (HT) resistant
OSP coating. The GC work performed in this study clearly shows the key organic components in the HT OSP coating that
affects solderability. The GC work also shows the alkyl benzimidazole-HT used in HT OSP is of the lowest volatility. The
accompanying TGA data also illustrates that the HT OSP coatings have a higher decomposition temperature compared to
existing industry standard OSP coatings. The XPS shows that HT OSP has only about 1% increase of oxygen content after
five Lead Free reflow cycles. In combination,these improvements are assessed relative to the industry needs to meet the
performance challenges of lead free soldering.

The advent of surface mount technology and now the lead free issue have ushered in a new wave of solderability treatments,
in particular the flat hard metal finishes. Among others these include electroless nickel immersion gold (ENIG),immersion
tin and immersion silver. All of these treatments are presently being used within the industry,but each has its own set of
issues. Recently a new coating has been introduced using electro plated nickel and gold. This coating was used by North
American suppliers in the 80’s,but lost its popularity with the introduction of Sn/Pb HASL.
Recently,a modified version of this technology has been resurrected,principally by Chinese PCB shops and is now being
offered at very competitive prices compared to the other hard metal finishes. The coating is referred to as “Flash Gold” and
consists of a soft gold over nickel structure. It is normally applied in a continuous electrolytic plating line. The discussion
below will describe the process and how it has been modified from the original process used by domestic shops two decades
ago.

Following previous reports by the authors on the general properties of a novel immersion silver process,this paper presents
the production experience in typical horizontal lines to demonstrate its robustness. In addition,several reliability issues
known to common immersion silver process are discussed; including galvanic attack,solder joint strength and BGA solder
joint integrity. It is found that galvanic attack is not necessarily caused by solder mask undercut,but is directly related to
silver thickness. The shear strength at the interface of both SnPb and SAC 305 alloy is independent of the silver thickness
(0.05 to 0.5 µm) and of Pb-free reflow treatment (up to three cycles). No “planar” micro voids that are detrimental to strength
and reliability are found in the BGA solder joints.

With the latest legislations from RoHS and WEEE dominating the horizon of the PCB landscape there is a need for
manufacturers and their suppliers to understand their impacts. The requirement to remove lead from the industry and
therefore the need for lead-free soldering operations means a large amount of stress is placed on the PCB substrates. The
laminate material suppliers are responding to the new legislation by introducing newer varieties of materials that have better
heat stress handling capacities as well as some added benefits like reduced z-expansion. Another concern for the laminate
manufacturers is the need to remove halogen based,flame retardants like bromine from their resin systems. This paper will
discuss the relevant legislations and the impact of these on the desmear and plating through hole processes. We will introduce
and discuss the changes that are taking place in the laminate materials sector needed to meet the newer requirements. We will
discuss the most significant advances in the halogen free as well as Pb-free capable materials. The significance of the changes
and their influence on the desmear and PTH processes will be highlighted. Test results from investigations and experiences
with the newer materials will be presented and compared to results normally found for the more standard materials. We will
propose options for handling the various issues arising from these new materials and so help to prepare PCB manufacturers
for the coming turbulence in the industry being generated by the new legislative demands.

When manufacturing printed wiring boards and assemblies it is often necessary to cover certain areas prior to soldering operations in order to avoid them being wetted with solder. Such areas may be gold contacts,gold-plated rotary contacts
multipoint connectors,carbon conductive touch-key contacts or even larger areas for which selective soldering and multiple
soldering is necessary (e.g. mixed assembly).
This covering can either be carried out out with heat-resistant tape or by using peelable solder masks which are usually
applied by screen printing to offer a very simple and yet cost-competitive coverage compared to tapes. However,the field of
application and requirements has grown enormously,with the latest challenge being compatibility with lead free soldering
processes and their increased processing temperatures.
After soldering,the masks are peeled off manually. Compared with the manual application of heat-resistant masking tapes,
peelable solder masks offer significant technical and economic advantages,e.g.:
• considerably less time- and cost-consuming application compared to adhesive tapes
• no difficult-to-remove adhesive residues
• automatable and reproducible register-true application by screen printing
• even difficult areas,such as gold-plated rotary contacts,can be covered and protected without any problems
• depending on the ink type also suitable for multiple soldering,reflow soldering and lead free soldering.

High Frequency and Lead-Free laminate materials are finding increased use in the PWB fabrication industry driven by end
user requirements for high-speed signal transmission and lead-free soldering temperatures. Along with these newer materials
has been the need for improved reliability. End users are continually pushing for thermal performance to exceed five solder
floats and exceed 300 cycles to failure on IST testing. The PWB industry,faced with ever increasing reliability requirements
compounded by the fact that these new resin materials are more difficult to desmear and metalize,have become more
concerned with plating adhesion to the copper interconnect and resin material. Concerns over interconnect defects and resin
adhesion of the copper are causing fabricators to reinvestigate their metallization technologies. The purpose of this paper is
to provide information on how to improve the adhesion of the copper deposit through a closer study of the critical success
factors influencing the metal adhesion to both the interconnect and hole wall. The research showed that the electroless copper
grain structure,plating rates and desmear parameters have a significant influence on PTH reliability. Specially designed high
layer count test vehicles were employed to quantify the adhesion and overall PTH reliability. The results were verified with
micro section evaluation after multiple solder float excursions and Interconnection Stress Testing (IST). This work validates
the necessity of the metallization process to improve the robustness of the PTH under high temperature conditions.

Solder joint void has been considered a typical phenomenon in electronics assembly. Voids are caused by entrapped gases
produced during flux volatilization during SMT,air entrapment in plated through holes and flux reaction with metal
contaminates during the assembly reflow process. The factors affecting void formation are complex and subjective. It has
been observed that BGAs with 2%Ag (62Sn36Pb2Ag) ball tend to create larger voids in reflow solder joints than eutectic
(63Sn37Pb) ball. This study investigates the effect of different process conditions on void formation in the eutectic and
2%Ag solder joints and their effect on long term (2nd level) reliability.
A series of test vehicle PCBs were populated for 2nd level reliability testing using three different BGA packages (165PBGA,
144PBGA,and 1657 FCBGA). A DOE was designed using three factorials; 1) BGAs were acquired with eutectic balls and
2%Ag balls,2) two reflow profiles were established,245C peak volcano-type profile with 3C/sec ramp and long soak profile
with 204C peak,3) two package preconditioning,60C/60%RH 10days and non-aged.
After SMT assembly test vehicles were x-ray inspected for void distribution and void size. X-ray results showed that large
voids,greater than 35% of the solder joint diameter according to IPC-7095A for class 2,were observed in both eutectic and
2%Ag solder joints assembled using large solder paste volume and reflowed using fast ramp rate to 245C peak temperature.
Approximately 60-250% higher distribution of voids was observed in 2%Ag ball packages than eutectic ball packages. It is
believed that the lower melting of 2%Ag (179C) solder ball can reflow slightly before the eutectic (183C) solder paste,thus
the solder ball collapses or encapsulates more solder paste/flux thus entrapping more gases within the bulk solder and
consequently promoting void formation. The effect of voiding on solder joint shock and thermal reliability was investigated
and discussed. It showed voids generated during board level assembly process do not degrade solder joint reliability.