The Electrical Wire Processing Technology Expo, (EWPTE), to be held in person at the Wisconsin Center in Milwaukee, Wis., May 10-12, is the exclusive showcase for the electrical wire harness, wire, and cable processing industries. Produced by the Wiring Harness Manufacturer’s Association (WHMA), IPC, and the Wisconsin Center District, EWPTE connects buyers with local, national, and international manufacturers and distributors. Registration for EWPTE is free.
In addition to a trade show with leading industry suppliers, EWPTE will host training and education opportunities for attendees, focused on continuous learning in cable and wire harness, with workshops, seminars, and conference sessions.
“EWPTE is a conference and exhibition geared toward decision makers who design, specify, purchase, install, sell, maintain or manufacture electronic cable assemblies, cord sets, wiring harnesses and other related products,” said David Bergman, WHMA executive director. “The 2022 in-person event will provide attendees with a new trade show experience with expanded networking opportunities and increased access to industry solutions.”
Free educational offerings include:
Tuesday, May 10
Wednesday, May 11
Thursday, May 12
EWPTE will also feature IPCSummerCom, IPC’s standards development committee meetings, to be held May 7-12. For more information on EWPTE, including full descriptions of educational content and to register, visit www.electricalwireshow.com. To learn more about IPCSummerCom, visit www.ipc.org/event/ipc-summercom.
The iNEMI/IPC/Fraunhofer Eco-Design for Circular Electronics Economy comprised a series of interactive webinars featuring industry leaders sharing their experiences in implementing innovative/beyond regulatory compliance eco-design work. The goal of this educational series was to capture the best and most innovative practices being used today and to highlight the processes these leaders follow to determine where to focus their eco-design efforts.
In reviewing the presentations from the webinars, the Eco-Design team identified several common approaches, or themes, regarding how the different organizations drive circular economy in their business models and products. As a final report, the team produced four videos that summarize these successful approaches. One video provides an introduction and overview to the series and three summarize the approaches identified as common themes in the presentations: https://youtu.be/PtEkaXd_Uk0
In recognition of their leadership roles and support of IPC standards, education, advocacy, and solutions to industry challenges, four of the industry’s best and brightest were presented with an IPC Rising Star Award at IPC APEX EXPO 2022. Award recipients were Tim Burke, Francisco Fourcade, Thomas Marktscheffel, and Christina Rutherford.
Burke, CTO and co-founder, Arch Systems, was honored for his active membership on the IPC-CFX committee A-team, advancing the ability of factories to collect and analyze machine data using “big data” and machine learning techniques. Burke works on implementing CFX in the field, helping to develop equipment for manufacturing facilities.
Fourcade, a master IPC trainer, was honored for his integral role in several IPC standards development committee A-Teams. A participant in the J-STD-001 A-Team, IPC-A-610 A-Team, Shock and Awe A-Team, Team Kangaroo, Team Iron, Team Bones, and the IPC/WHMA-A-620 Training Committee A-Team, his commitment enabled all teams to fully participate in discussions.
Marktscheffel, a product manager at ASM Assembly Systems, Germany, was honored for his expertise in smart factory implementation, supporting global industry standards such as IPC-CFX and HERMES to provide plug and play connectivity for SMT smart factories. Marktscheffel currently serves on 13 IPC standards development committees.
Rutherford, a materials and process engineer at Honeywell Aerospace, was honored for her leadership of Team Bones, a sub-team developing x-ray guidelines for IPC/WHMA-A-620 for cable and harness. Rutherford, a third-year IPC emerging engineer, serves as a member of the IPC-A-610 A-Team committee, is an IPC scholarship reviewer, and was recently named vice-chair of the 5-24G Polymerics Standard Task Group developing IPC-5262, Design, Critical Process and Acceptance Requirements for Polymeric Applications.
“The leadership shown by our Rising Star recipients has made a significant impact on IPC and will do so for years to come,” said John W. Mitchell, IPC president and CEO. “We are privileged that Tim, Francisco, Thomas and Christina have chosen to share their knowledge and expertise with us and with the entire global electronics manufacturing industry.”
The inaugural IPC Design Competition at IPC APEX EXPO 2022 resulted in a win for Rafal Przeslawski, Xilinx, whose printed circuit board design earned him the top prize.
In late 2021, printed board design engineers from around the world were invited to compete in IPC’s inaugural PCB Design Competition. Intended to be accessible for anyone with a design tool and an internet connection, this new competition would challenge designers in two heats: an at-home, 30-day full board build, and an ‘in-person’ four-hour routing challenge at IPC APEX EXPO 2022.
In the preliminary heat, 14 designers from all corners of the globe – from India to the Netherlands; Oregon to the United Kingdom – were provided with a schematic, a component BOM, and scope of work document, and were asked to design a board that was compliant with IPC’s various board design standards. The given schematic was representative of a motor control board that included features intended to test the competitors’ understanding of various design methodologies.
Out of 14 preliminary competitors, three finalists were chosen to compete at the finals: Elliot Wakefield, a hobbyist based in the United States, Nick Wallis, an electronics engineer at Tribosonics in the United Kingdom, and Rafal Przeslawski, a hardware development engineer at Xilinx based in Germany.
The finals heat took place at IPC APEX EXPO 2022. The competitors were challenged to complete the design of a nearly complete board – missing only design rules, routing, and a few components left in the margins. “With only four hours to do so, completing the board was a careful balance of thoughtful component placement optimization and design rule definition, and brass-tacks routing,” explained Patrick Crawford, manager, design standards and related industry programs. “The board design was that of a functional, programmable blinky-badge that was actually fabricated and on display at IPC APEX EXPO. In other words, unlike the preliminary heat, the final design was representative of a real-world, functional application.”
At the end of the four hours, each competitor delivered their project file to the judges, who deliberated for two hours, ultimately crowning Rafal Przeslawski as the IPC Design Competition 2022 champion.
PCB designs are quoted and fabricated every day. Most of the released designs will have engineering questions (EQ’s) also called technical queries (TQ’s) in Asia. These questions are generated once the data package has been received and analyzed. This back and forth has been the accepted data transfer methodology for decades.
CAD software and their associated DFM software packages have not been able to resolve this issue. Contributing factors include the reluctance of fabricators to provide their design rules due to IP concerns and the common practice of sending non-intelligent data along with conflicting documentation.
So, until the design-to-fabrication design transfer environment makes a revolutionary leap, there is a manual method for reducing data transfer issues. As Michael Jordan’s quote references, we have lots of talent on both sides working as a team. Let us focus on the intelligence aspect to create a championship.
State the Problem: The problem is "EQs are being generated for all or some designs post delivery to the fabricator." Both sides of the transfer need to agree that this is an important problem or there is no need to proceed. My experience has shown that it is most successful when this problem is presented by the fabricator to a customer.
Set Goals: Create two KPI goals to reduce the number of EQ communication cycles by 50% within 6 months. This is most successful when the KPIs are added to both the design team and fabricator front-end engineering team’s performance goals. This puts some skin into the game at both ends.
Collect and analyze the data: The fabricator should review all the designs received over the prior six months. Log the part numbers, design center locations, if known, the number of EQs generated for each part number and each revision of that part number (include any pre-design DFM's that were performed), number of EQ comment back-and-forth cycles, and then create a spreadsheet with each EQ issue. Pareto out the EQs by part number and revision, EQ quantity by type.
The customer can take the data and Pareto it out by the designer, project, design location, etc. They can also collect data from all their suppliers to compare the EQs that were noted, or not noted. For example, part number Z is built by a local quick-turn shop and then transferred to high-volume shops in Asia. There may be issues not noted by the QTA shop that the volume shops note.
Process improvement: Don’t’ try to solve every issue at once. Apply the 20/80 rule. Update the customer fabrication/acceptance specification and design electrical/mechanical requirements that can be adjusted. Customers can review where the design conflicts with their acceptability specification, review data output translation issues, etc. Fabricators should review their quality data to see where they have sufficient capability margin to allow a wider design rule to be used for EQs where the customer states that the request cannot be accepted. This is where the fabricator provides more knowledge to the customer about their process capability than prior communications. Items in this document will not require an EQ for future designs since they will have global approval.
Create a Global Deviation Document stating where both sides agree to changes of their existing procedures or capabilities. For example, approval for non-functional pad removal can be included in this document. The best solution is where the OEM can create one document that can be applied to all suppliers to keep it simpler for the designer and continue to monitor EQs over the next six months and review the results against the KPI of a 50% reduction in EQs, then repeat the process for more improvement.
Conclusion: Teams I've been part of have successfully run this project with multiple large and small companies around the world. The design team becomes more efficient because they do not have to stop work on their new design to address issues on the previous design. The fabricator gains substantial net capacity because the designs flow through planning/CAM and get to the production floor faster. This manual EQ reduction method will create championships by reducing design costs and attracting additional revenue for the fabricator because it will be easier to work with you versus a competitor.
Dana Korf is the principle consultant at Korf Consultancy LLC. A previous version of this article appears in his column Dana on Data at PCBDesign007.
"Talent wins games, but teamwork and intelligence wins championships." ~ Michael Jordan
Hundreds of PCB designs are released to be quoted or fabricated every day around the world. Most of the released designs will have engineering questions (EQ’s), also called Technical Queries (TQ’s) in Asia, generated once the data package has been received and analyzed. This is the accepted data transfer methodology, as it has been even before disco music was invented (and thankfully disappeared). CAD software and their associated DFM software packages have not been able to resolve this problem by getting in sync with fabricator and assembler DFM/quoting software and rules. This is due in part to fabricators not providing their design rules due to IP concerns. It is also due, in part, due to the common practice of sending non-intelligent data along with conflicting e-paper documentation (e.g. fabrication prints).
So, until the design-to-fabrication design transfer environment makes a revolutionary leap, there is a manual method which can reduce data transfer issues. As Michael Jordan’s quote references, we have lots of talent on both sides. We have teamwork resolving the issues. Let us focus on the intelligence aspect to create a championship.
Lets’ use a fundamental Lean/Six Sigma based concept: First: Establish the problem. Second: Establish the goal. Third: Collect and analyze data. Fourth: Improve the process. Fifth: Update procedures and training. Sixth: Declare victory. Seventh: Go back to step 2, update the goal and keep the project alive until no EQ’s are generated.
Establishing the methodology is the easy part, so how can this be performed?
Establish the problem: The problem is “there are EQ’s being generated for all or some designs that are received by the fabricator”. Both sides of the transfer need to agree that this is an important problem or there is no need to proceed. My experience has shown that it is most successful when this problem is presented by the fabricator to a customer.
Establish the goal: Create two KPI goals to reduce the number of EQ’s and EQ communication cycles by 50% within 6 months. This is most successful when the KPI’s are added to both the design team and fabricator front-end engineering team’s performance goals. This puts some skin into the game at both ends.
Collect and analyze the data: The fabricator should review all the designs received over the prior six months. Log the part numbers, design center locations, if known, how many EQ’s were generated for each part number and each revision of that part number (include any pre-design DFM’s that were
performed), number of EQ comment back-and-forth cycles, and then create a spreadsheet with each EQ issue. Pareto out the EQ’s by part number and revision, EQ quantity by type.
The customer can take the data and pareto it out by designer, project, design location, etc. They can also collect data from all their suppliers to compare the EQ’s that were noted, or not noted. For example, part number Z is built by a local quick-turn shop and then transferred to high volume shops in Asia. There may issues not noted by the QTA shop that the volume shops note.
Process improvement: Don’t’ try to solve every issue at once. Apply the 20/80 rule. Most of these analyses will have 20% of the problems generate 80% of the total EQ quantity. Update customer fabrication/acceptance specification and design electrical/mechanical requirements that can be adjusted. They can review where the design conflicts with their acceptability specification, review data output translation issues, etc. Fabricators should review their quality data to see where they have sufficient capability margin to allow a wider design rule to be used for EQ’s where the customer states that the request cannot be accepted. This is where the fabricator provides more knowledge to the customer about their process capability than prior communications. Items in this document will not require an EQ for future designs since they will have global approval.
A global deviation document can then be generated stating where both sides agree on changes to their existing procedures or capabilities. For example, approval for non-functional pad removal can be included in this document. The best solution is where the OEM can create one document that can be applied to all suppliers to keep it simpler for the designer.
Concurrence at this point is where the intelligence is created to win this championship. You have now achieved step Six, where the team declares victory.
The fabricator can monitor the pareto results for design transfers over the next six months. Generate a new analysis and present it to the customer. If the 50% reduction has been achieved, resent the level down another 50% and continue the project until 80% of the design transfers achieve the zero EQ goal.
Teams that I have been involved in have successfully run this project with multiple large and small companies around the world. The design team becomes more efficient because they do not have to stop work on their new design to address issues on the prior design. The fabricator gains substantial net capacity because the designs flow through planning/CAM and get to the production floor faster.
This manual EQ reduction method will create championships by reducing design cost and attracted additional revenue for the fabricator because it will be easier to work with you versus a competitor.
Dana Korf
Principle Consultant
Korf Consultancy LLC
Bremerton, WA
dana.korf@korf.com
www.korf.com
The electronics manufacturing industry is welcoming the release of the European Commission’s European Chips Act with its strong support for advanced packaging and calling for its swift implementation as part of a broader and equally important strategy to rebuild the European electronics manufacturing ecosystem.
In its proposal, the Commission proposes robust public and private investment in chip fabrication as well as semiconductor packaging. Today, in a post-Moore’s Law environment, electronic interconnection within the package is key to realizing more advanced functionality and economic efficiencies in chip designs. Pairing investments in advanced packaging with investments in chip fabrication is necessary to technological innovation and greater supply chain resiliency.
“The Chips Act is critically important in ensuring a sustainable supply of cutting-edge chips for Europe’s electronics manufacturers and strategic industries,” said IPC President and CEO John W. Mitchell. “However, chips don’t function in isolation; they require interconnection with other components via printed circuit boards and PCB assemblies, which are mostly built outside of Europe. To meet the goals of the Chips Act, Europe needs to take a comprehensive approach to bolstering the region’s electronics manufacturing ecosystem.”
IPC has been a leading European voice for a “silicon-to-systems” approach that recognizes the strategic importance of printed circuit board (PCB) fabricators and electronics manufacturing services (EMS) companies. Last April, IPC released a detailed analysis of Europe's strengths and vulnerabilities in these critically important sectors as well as policy recommendations to boost the resilience and competitiveness of the industry in Europe.
Electronic systems are essential to every industrial sector across Europe’s economy and key to delivering on Europe’s digital and green transitions. And yet, the Chips Act perpetuates a far too narrow, triage-like approach to technological innovation focused almost singularly on one segment of the electronics manufacturing ecosystem to the exclusion of the ecosystem upon which it depends. A viable, long-term strategy for innovation and economic growth requries a strong foundation of European electronics manufacturing which largely remains marginalized in the region’s industrial policies.
Alison James, IPC’s Senior Director for European Government Relations notes, “The European electronics value chain has strategic gaps and vulnerabilities which include, but are not limited to, semiconductors. Now more than ever, it is vital that chip investments are made within the framework of a broader strategy designed to strengthen the region’s electronics industry through all its constituent parts.”
IPC has been making the case to European policymakers that there is a real opportunity now for the EU to deliver on the full potential of the Chips Act by also fostering needed investments in the crucial supply chain including R&D, Packaging, specific equipment, new PCB and EMS facilities and a skilled and educated workforce across the chain. A holistic approach to the sector is needed to ensure future innovation, resiliency, and security.
IPC looks forward to working with the European Institutions and Member State Governments to implement the Chips Act and to augment it with much needed support for the related industries upon which semiconductor manufacturers rely. IPC calls attention to building Europe’s capacities throughout the electronics value chain, the importance of technological sovereignty without losing sight of working closely with strategic partners to obtain the required resiliency in all supply chains dependent on electronics.
In recognition of their significant contributions of time, talent, and ongoing leadership in IPC and the electronics industry, Susann Chen, Joe Kane, and John Walls were presented with IPC President's Awards at IPC APEX EXPO on January 25.
Susann Chen, ZhuZhou CRRC Times Electric Company, serves as chair of IPC ASSC, chair of IPC/WHMA-A-620C-Rail Transit Addendum, co-chair of 7-31f China Task Group, vice-chair of IPC-A-610G Rail Transit Addendum, and as a member of IPC TAEC-Global. Chen was honored for her work with IPC China to convene technical conferences and competitions, to promote in-depth cooperation between IPC and the rail transit industry in China, and for encouraging participation in IPC training and events.
Joe Kane, BAE Systems, chair of the D-35 subcommittee, was honored for serving on 21 standards development committees, helping to write the original IPC-1601 and Rev. A guidelines, and most recently IPC-1602, Standard for Printed Board Handling and Storage, and IPC-7801A, Reflow Oven Process Control Standard.
John Walls, Aegis Software, was honored for being an early promoter of the Industrial Internet of Things standardization that led to the IPC-2591 Connected Factory Exchange (CFX) committee, and the historic launch of the IPC CFX IIoT standard. Walls engineered the CFX toolkit and is the architect of the IPC-CFX qualification website and cloud engine, contributing to the content that formed the IPC-CFX education courses.
“We are happy to present the President’s Award to Susann, Joe, and John, in appreciation of their significant contributions to IPC and the global electronics manufacturing industry,” said John Mitchell, IPC president and CEO. “Their leadership and expertise set the standard for building electronics better.”
Three IPC volunteers who have fostered a collaborative spirit, made significant contributions to standards development, and have consistently demonstrated a commitment to global standardization efforts, were presented with Dieter Bergman IPC Fellowship awards at IPC APEX EXPO 2022. Bev Christian, Doug Pauls, and Jose Servin were chosen as award recipients because they embody the work ethic and spirit of the late Dieter Bergman, a pioneer and industry icon. They will bestow Dieter Bergman Memorial Scholarship awards on the university or college of their choice.
Bev Christian, Ph.D., a facilitator for the High-Density Packaging User Group and Adjunct Professor at the University of Waterloo, Canada, has participated in IPC APEX EXPO since its inception. A member of 27 committees, including co-chair of the 2021-2022 Technical Program Committee, Bev serves as chair of the 3-11G and 5-24B task groups. An author of more than fifty published papers, Christian chose the Chemistry Department at the University of New Brunswick, Fredericton, New Brunswick, Canada, as the scholarship recipient.
Doug Pauls, a dedicated volunteer at IPC, was awarded the IPC Hall of Fame in 2017. A principal materials and process engineer at Collins Aerospace and former chair of several IPC committees, Pauls is known for his expertise in surface insulation resistance testing, cleaning and cleanliness assessment, conformal coatings, and how to investigate and qualify manufacturing processes. He recently led the team that redefined the cleanliness provisions of IPC J-STD-001, culminating in what is presently J-STD-001G, Amendment 1. Pauls’ school of choice for the Dieter Bergman scholarship is the Materials and Science Engineering (MSE) department at Iowa State University in Ames, Iowa.
Jose Servin Olivares is a level three senior process engineer at Vitesco in Mexico who specializes in electronics assemblies in SMT, BE, and electronics component manufacturing. A member of the IPC-A-610 and J-STD-001 working groups and former chair of the IPC-A-610G and J-STD-001G Automotive Addendums, he worked closely with the committees to address criteria and acceptability requirements for printed board assemblies for the automotive industry not covered in IPC-A-610G and J-STD-001G. Servin Olivares chose a branch of the Morelos State University in Mexico as the recipient of the Dieter Bergman award – Yecapixtla School of Higher Studies of Morelos State University.
“The recipients of this year’s Dieter Bergman Fellowship award have devoted years to IPC standards development, and we are fortunate to be the recipients of their considerable talent and expertise,” said John W. Mitchell, IPC president and CEO. “We are glad to be able to honor their volunteerism and assist future engineers with this award.”
From revolutionary innovations displayed on the show floor to expert insights conveyed in technical conference sessions, professional development courses and standards development committee meetings, IPC APEX EXPO 2022 provided the education and networking connections that helped 3,647 visitors address today’s business challenges and prepare for their factories of future.
In keeping with the event’s theme, “Lead, Drive, Achieve Digital Transcendence,” IPC APEX EXPO’s technical conference featured 104 technical papers detailing original research and innovations from industry experts around the world and opportunities for learning abounded. For 2022, IPC’s Technical Program Committee expanded the conference to four tracks of high-quality, peer-reviewed content from 18 countries, setting a very high bar for the papers delivered. Those four tracks focused on factory of the future implementation; PCB fab and materials; quality, reliability, test, and inspection; and assembly materials and environment.
Nearly 100 standards development committees made significant progress on new and revised documents including IPC-J-STD-001, IPC-A-610, IPC-7711/21, IPC/WHMA-A-620, IPC-2551, IPC-2591 and dozens more. “At the joint IPC J-STD-001 and IPC-A-610 task group meeting, more than 90 volunteers contributed their expertise to revising the standards,” said Teresa Rowe, IPC senior director, assembly and standards technology. "At times, discussions were spirited, but great headway was made on the 'J" revisions.
Many attendees achieved their business objectives at the event. “Attending IPC APEX EXPO is the most efficient way to learn about new equipment and processes that can help make my job easier,” said Randy Bremner, Northrop Grumman. “All the experts are there; we were able to meet in person this year and I got all of my questions answered in one place. It’s truly one-stop learning in classrooms and shopping on the show floor.”
The APEX EXPO 2022 experience was equally positive for the 282 exhibitors who showcased their products and services on 108,300 square feet of show floor space. “Our team feels this was the best IPC APEX EXPO we have participated in,” said John Lee, Insulectro. “Yes, due to COVID, attendance was a little light, but we had top quality opportunities to meet with customers, prospects, and suppliers. We were all blown away with how effective and productive APEX EXPO was for us.”
Added Jason Spera, Aegis Software, “It was great being back at APEX EXPO live after a two-year break. Our experience at this year’s show was much better than anticipated. We came to the show enthusiastic but wondering frankly what would happen and how things would go, but IPC did a brilliant job handling this year’s event. The attendance at our booth was far in excess of what we expected.”
Said John W. Mitchell, IPC president and CEO, “The January omicron surge provoked more than a few questions about what to expect at this year’s IPC APEX EXPO. As I traversed the San Diego convention center last week, the answer was clear, a lot of smiles. Yes, they were hidden behind masks but more than evident in the eyes of everyone with whom I interacted. Attendees were thrilled to back together in-person—sharing ideas as freely as elbow bumps. IPC is a community and IPC APEX EXPO is the place we build it. It was great to be back!”
In 2023, IPC APEX EXPO will return to the San Diego Convention Center, January 21-26. For more information, visit www.ipcapexexpo.org.