The development of nano-scale surface finishes over copper pads such as Electroless Palladium and Autocatalytic Gold (EPAG) has been evolving in the recent years due to ever increasing demands in terms of reliability, component miniaturization and signal transmission.

Scope of this paper is a full investigation of the production reliability of Electroless Palladium and Autocatalytic Gold. As soldering and bonding are both possible with EPAG and of special interest in the microelectronics industry, the solder joint reliability (SJR) and bonding results will be evaluated. Increasing I/O counts have led to ever decreasing cross sectional contact areas or, by default, an increase in solder performance expectations. The evaluation of this high solder joint reliability demand was satisfied by cold ball pull testing and high-speed shear testing (HSS).

To examine EPAG’s bonding abilities, the as-received (ASR) mode, as well as the aged condition at 150°C for 4h, were applied. Also, general storage reliability of the EPAG finish was simulated via ageing for 100 to 1000 h after bonding, assessing EPAG’s bonding performance over a broad process window. EPAG’s gold wire bond performance will be rated against ENEPIG finish. In addition to soldering and bonding, the reliability of a final finish is also reflected in its wetting behavior and adhesion; therefore, solder indicator, dewetting and solder spread testing were performed. Reliability against external, harsh conditions was tested via salt spray testing and compared to other common final finishes.

Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) is a well-accepted and established finish for high performance applications. The properties of the coating are determined mainly by the characteristics of the palladium layer and the type of the gold electrolyte used and have been investigated in various studies. 

In general, PdP or pure Pd coatings are available, which differ not only in their coating properties but also in their plating behavior and in the properties of the electrolytes used. The subsequent gold layer might be deposited by either an immersion type electrolyte or alternatively a reduction assisted gold bath which also will impact the final layer properties.

Looking back on a long experience of ENEPIG plating with pure Pd as well as with PdP, this paper will focus on the comparison of pure Pd and PdP deposits and the interaction with the gold electrolyte type in use.  The initial start reaction of the Pd bath is studied and the difference in the behavior of the PdP and pure Pd electrolyte was compared. Knowing that the crystallinity of the deposited layer is different for a pure Pd deposit compared to a PdP layer, the porosity was determined with the help of electrochemical as well as microscopical techniques to identify and judge the probability of a corrosive attack of the gold electrolyte to the underlying nickel. To be able to reliably judge the corrosive attack of the gold electrolyte, the corrosion was statistically evaluated by rating the number of corrosion events as well as the depth in the nickel deposit.

When comparing the performance of the finishes, considering the properties of electrolytes and the plating conditions, it becomes obvious that there is no single solution for all requirements. Rather, that the process allows manifold options to define the best conditions to the customer needs.

Key Words ENEPIG; Corrosion; Porosity; Solder Joint Reliability

The evolution of internet-enabled mobile devices has driven innovation in the manufacturing and design of technology capable of high-frequency electronic signal transfer.  Among the primary factors affecting the integrity of high-frequency signals is the surface finish applied on PCB copper pads –a need commonly met through the electroless nickel immersion gold process, ENIG. However, there are well-documented limitations of ENIG due to the presence of nickel, the properties of which result in an overall reduced performance in high-frequency data transfer rate for ENIG-applied electronics, compared to bare copper.

An innovation over traditional ENIG is a nickel-less approach involving a special nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer. In this paper, assemblies involving this nickel-less novel surface finish have been subjected to extended thermal exposure, then intermetallics  analyses, contact/sheet resistance comparison after every reflow cycle (up to 6 reflow cycles) to assess the prevention of copper atom diffusion into the gold layer, solder ball pull and shear tests to evaluate the aging and long-term reliability of solder joints, and insertion loss testing to gauge whether this surface finish can be used for high-frequency, high density interconnect (HDI)applications.

Key words: surface finish, ENIG, nickel-less technology, high reliability, robust solder joint, intermetallics.

QFN-Quad Flat No-lead SMT-surface mount technology components continue to be increasingly used and also becoming smaller for applications further requiring a high level of thermal performance and reliability.  QFN device thermal pad regions have been observed w/ excessive void densities >30% in area, which limits the thermal conductivity or performance of the device and often requires subsequent costly rework.  Voids also become more dominant for smaller devices as the surface area of the thermal pad regions decrease, but voids may not correspondingly reduce in size or density. Using various reflow profiles, solder paste volumes and over-print values showed a statistically significant reduction of large voids and void density using the solder paste over print method. In addition, void formation and escape paths were demonstrated using x-ray imaging technology equipment that can be programmed to simulate an actual SMT surface mount technology reflow profile on a thermal platform or hot plate and provide real-time X-ray imaging recording the materials physical and void behavior.

Voiding in solder joints has been studied extensively, and the effects of many variables compared and contrasted with respect to voiding performance. Solder paste flux, solder powder size, stencil design, circuit board design, via-in-pad design, surface finish, component size, reflow profile, vacuum reflow, nitrogen reflow and other parameters have been varied and voiding quantified for each. The results show some differences in voiding performance with respect to most of these variables, but these variables are not independent of each other. Voiding in solder joints is a complex issue that often requires multiple approaches to reduce voiding below required limits. This paper focuses on solutions to voiding for commonly used bottom terminated components (BTCs).

When voiding is an issue, it is often not possible to change the solder paste or circuit board design due to end user requirements and time constraints. It is much easier to change the stencil design and the reflow profile in an effort to reduce voiding, and this can be done in a timely manner. Stencil design and reflow profile can be used to minimize voiding for BTCs like Quad Flat No Lead (QFN) components. Optimization of the windowpane size and web width can help with voiding. Changing the volume of solder paste on the I/O perimeter pads of QFNs also has an effect on voiding. Use of linear ramp-to-spike (RTS) reflow profiles reduces voiding with some solder pastes, while ramp-soak-spike (RSS) profiles work better for other solder pastes. Stencil design and reflow profile were optimized for a variety of QFN components in order to minimize voiding. The results of this testing were quantified, summarized and recommendations given for ideal voiding performance.