All electronics products need a power source. Thereby power electronics has a fundamental impact on their design and integration, from materials and device up to systems and the applications they serve. They do this via a number of different paths, whether it be driving the bleeding edge of system size, weight, and power (a.k.a. – SWaP) specifications or determining the viability of battery-powered applications from autonomous vehicles to Internet of Things (IoT) little gadgets. The success of a system or product deployment is not only heavily dependent on the integration of intelligent power management (IPM) and shrinking size of its power supplies, but also how those power solutions interact with system loads and energy storage to optimize utilization for energy efficiency.

The session comprises three papers presenting a wide overview of the electronics market as seen through the lens of power electronics by focusing on three major areas of coverage, namely ‘power IoT’, energy storage and smart mobility, focusing primarily on IoT but the concepts and consideration being broadly applicable to a broad range of applications. Having a finger on the pulse of where power electronics industry stakeholders are headed is essential to maintaining a view on the horizon for what is technically achievable to form realistic expectations of application-driven marketing projections.

From automotive to semiconductor manufacturing, the bottlenecks for what is achievable are typically gated by power supply component size, form factor, and weight. From the perspective of power electronics, this mostly boils down to the power supply topology chosen, which can dictate switching frequency and therefore the minimum electrical/thermal requirements for key, passive components such as magnetics and capacitors. Given the broad range of skills, experience and expertise of the target audience, the technical details regarding things like topology selection and lower-level requirements will be abstracted into far simpler project requirements and drivers that directly impact passive component physical characteristics (e.g. – SWaP). The presentations attain to insight on how to translate seemingly complex power supply characteristics and bleeding-edge application needs into relatable information for their own area of focus, which can be brought back to teams and easily communicated to a broad range of stakeholders.

Driven by the demand for advanced electronic devices where massive wireless data transfer is required, a new generation of communication system, so called 5G has been developed. This new technology isnow fully introduced to the market and will continue to rapidly expand due to very high demand. One of the key features in this technology is the capability of devices to transmit high volumes of data in high frequency bandwidth. Given the nature of the path of the electronic signal in highly conductive medium such as copper, as the signal frequency increases, the impact of the conductor roughness and the so called “skin effect” results in an increase of resistance. This brings a greater risk of compromising the signal integrity due to increased signal loss; in order to minimize the signal loss, it is highly desirable to keep the conductor profile as smooth as possible. This is considered as an absolute requirement. Therefore, the previous technique of creating adhesion between conductors and dielectrics by surface roughening is not suitable anymore. The ideal way to overcome this challenge would be to use a bonding enhancement system which does not require surface roughening. This study demonstrates the development of a novel surface treatment system for copper which can meet all of the challenges of electronic devices manufactured for high frequency applications. The surface treatment systems introduced here adopted the use of a subsequent treatment of organic coating, a so called “adhesion promoter” on top of pre-cleaned copper surface, to provide the strongest possible bonding strength. As a result,significant improvement of adhesion between copper conductor and lamination material can be obtained at very low surface roughness. This can be explained by the increased contribution of chemical bonding provided by the organic coating. Furthermore, superior thermal reliability can also be achieved. Since a minimal surface roughness has been created by the process, a significantly lower signal loss could also be obtained. The system introduced here offers the best approach for surface treatment process of high- speed IC substrate manufacturing.

Key words High frequency, skin effect, adhesion promotor, signal integrity, IC substrate

The electronic packaging industry is undergoing a revolutionary convergence between the printed circuit board segment and the semiconductor packaging segment. New, streamlined and hybrid package architectures are emerging to meet future product requirements – particularly for mobile electronics and infrastructure to support industry megatrends like 5G. There are new challenges for forming electrical interconnections between different types of package elements while maintaining high volume manufacturability and reliability.

In particular, the use of high speed and high frequency dielectric materials complicates the PCB fabrication process. Generally, these low loss and low Dk materials are not amenable to multiple lamination cycles due to the nature of their chemistry; however, conventional PCB fabrication techniques that circumvent this problem by using plated-through-holes introduce undesirable resonance structures and consume precious real estate that could otherwise be used for routing.

Transient liquid phase sintering (TLPS) paste vias can be used to either augment or replace sequentially formed plated microvia interconnects, which necessitate multiple lamination cycles, as well as plated-through-holes (PTH) with their attendant loss of routing density and lossy stubs. TLPS-filled z-axis interconnect layers can be fabricated in parallel with individual x-y trace layers or PCB subconstructions of multiple layers with PTH, interleaved, and laminated in a single cycle. The circuit layers thus electrically joined through the z-axis can be of the same or different materials, complexity and native construction. The adhesive surrounding the TLPS interconnects and mechanically joining the circuit layers can be prepreg or film adhesive and be selected for its adhesive, dielectric and mechanical characteristics. With an appropriate adhesive layer, the TLPS z-axis interconnect concept is extendable to applications outside of PCB construction including area array assembly and thermal transfer.

TLPS pastes, which metallurgically bond to circuit pads, offer both high performance and versatility of installation that is conducive to high manufacturing volumes. Because sintering pastes can be formulated with a variety of particle sizes and flow behavior this technology can provide a spectrum solution to applications from filled microvias in either a printed circuit board or semiconductor package scale, to printed bumps for interconnection of subassemblies, to thermal interfaces with embedded heat sinks.

This paper will present the two most common implementation flows for the installation of the TLPS paste z-axis interconnects in mixed mode PCB constructions.

In many aerospace and defense systems, there are increasing demands for multi-functional adhesive solutions that not only fulfill the traditional role of component and assembly bonding, but also offer additional features to address electrical and thermal requirements to improve device reliability. Developing robust adhesives that encompass all these characteristics can be quite challenging.

Broad adoption of wide-bandgap (WBG) semiconductors (i.e. gallium nitride (GaN), silicon carbide (SiC), etc.) combined with diverse accessible heterogeneous integration (DAHI) technologies are transforming power electronics system design and assembly processes. The power requirements of these systems -- especially military electronic systems such as surveillance, airborne multifunction radars, communication systems, directed energy systems, etc. are increasing dramatically. Consequently, the necessary heat dissipation of such electronic devices has already reached several thousand watts/cm2 at chip level and is projected to grow exponentially. While already a critical element of system design, heat management has become even more important as power densities rise.

This paper presents a multi-functional solution for assembling high power density electronic devices that can manage heat, provide electrical isolation, tolerate large surface topography nuances up to 5 mil (the rest of the paper uses metric units – change?), and improve solvent and moisture resistance. Data will be presented highlighting these various properties along with details regarding reliability improvements.

Power electronics based on silicon devices must operate below 125 C and IGBTs under 150 C - WBG devices could extend this to 200 C. Thermal management of power electronics, whether power supplies or power components, requires interfacing the package to a heat sink using a thermal interface material (TIM). Traditionally used thermal greases provide good end of line performance but they can degrade. TIMs come in a wide variety of properties, physical formats and automation readiness to suit the wide variety of applications. Additionally, TIMs may be tasked with insulation reliability, adhesion and encapsulation. We will discuss thermally conductive solutions including greases/gels, liquid and solid gap fillers as well as metal core PCBs and their use in cooling power electronics – with reference to performance, reliability and manufacturing.

For many years, metals have been used as thermal interface materials (TIMs) in the electronics industry. With high reliability and high thermal conductivity, metals have been a great solution, especially for challenging applications. Thermal properties of any TIM are defined by their thermal conductivity and interface resistance. The biggest obstacle for metal TIMs to overcome is interface resistance. Because most metals are very stiff, a certain amount of pressure needs to be applied to form a close connection between the materials, thus lowering interface resistance. As electronic devices are continually getting smaller, consuming more power, and producing more heat, finding the right TIM becomes one of the top priorities in any application. Solid liquid hybrids (SLHs) are the next generation of metal TIMs. SLHs are a combination of metals that are solidus at room temperature with ones that are liquidus at room temperature. With low thermal resistance and low bondline thickness, SLHs are the perfect solution for certain high-end applications. This paper will discuss the possible applications where SLHs can be used, as well as challenges and obstacles that still need to be overcome to encourage adoption across the industry.

Despite its introduction over three decades ago, designing, manufacturing and testing of high-density interconnect printed circuit boards remains a topic of discussion. The introduction of HDI technology for space applications and the pursuit for qualification by the European Space Agency create the need for a critical review of existing test methods. For PCB procurement, qualification and process monitoring, ESA has gained significant heritage with interconnection stress testing. IST test parameters for mechanical vias and microvias are defined in the current PCB standards from ESA. Especially for microvias, recent experiences with failures have led to a revision of the test method. The revised test method has been applied to assess the so-called basic HDI technology, consisting of two levels of staggered microvias. The design of the IST coupons, including the placement of the microvias, is representative of the fanout routing for area array devices with 0.8 mm and 1.0 mm pitch. IST coupons are procured from four space-qualified PCB manufacturers and submitted to buried via and microvia testing separately. No failures are observed for the microvias from any of the manufacturers after 1000 cycles to 210 °C. The buried via endurance when cycling to 170 °C strongly varies between manufacturers. Resistance measurements and electrical monitoring during testing are applied to help explaining these variations.

The ENIG finish is one of the most common final finishes finding broad acceptance in the market for decades. ENIG is the abbreviation for “electroless nickel – immersion gold” where it is the nature of the gold plating step to include an immersion reaction. Even with conventional and simple immersion gold electrolytes having a high degree of displacement reaction, the resulting Ni corrosion does not necessarily cause issues in the solderability or reliability of the coating. Nevertheless the corrosive attack is seen as a critical parameter mainly driven by OEM’s so that acceptance criteria are defined in the latest version of the IPC 4552.

Key target for the development of immersion gold electrolytes is therefore always, to create a solution with lowest possible corrosive attack. Avoiding the creation of wide areas of surface corrosion, which might cause defects in soldering and bonding applications is obligatory. Over the recent years different generations of electrolytes were developed which differ in the plating mechanisms and the corrosion performance that can be achieved.

In this paper it is shown and described, which types of gold electrolytes are available in the market and what their characteristic corrosion attack look like. To allow a proper base line definition, this was done based on a thorough hypercorrosion evaluation. It is discussed, which types of corrosion can be really critical for the final application and where to focus on in the evaluation. Aim of this study is to compare the different types and generations of gold electrolytes and compare them in regards to handling, performance and reliability of the final finish

This study has been supported by a leading global PCB manufacturer allowing representative results and a comprehensive insight into the status of ENIG corrosion at the manufacturing process.

Key Words ENIG, Nickel Corrosion, IPC 4552, Immersion reaction

Field Programmable Gate Arrays (FPGA) allow customers the flexibility to configure devices after they have been manufactured. The demand for higher speed requires higher pin counts to provide greater functionality of the different I/O blocks in optimized FPGA devices. In order to achieve faster speeds, back drilling will be required for finer pitch FPGA PCB designs. Back drilling is the process whereby plated through holes (PTH) are drilled from the bottom of the PCB with a larger drill diameter (i.e. back drill) to a specified depth in order to reduce the stub length for improved signal integrity performance by minimizing interference or signal loss from excess travel length. Current industry back drilling capabilities have supported 1 mm pitches with minimum drill to metal spacing greater than 0.150 mm. For 0.92 mm pitches, signal layers require a 0.050 mm overlap between ground layers in order to avoid crosstalk from adjacent signal layers. Having a 0.050 mm overlap in the design means that the drill to metal spacing will need to be reduced to less than 0.150 mm. This in turn means that primary drill diameters, trace widths, and spaces will also need to scale down. These changes pose manufacturability challenges with primary drill (PD) registration and higher aspect ratios (i.e., PCB thickness/PD = ~5 mm/0.25 mm = 20/1). Reduced spacing compounded with drill registration issues can result in exposed copper, slivers/clipped traces, and layer-to-layer misregistration due to lack of PCB manufacturing experience with these finer pitches. Next generation FPGA platforms will push the limits of the PCB industry’s current capabilities, creating a need to identify and provide solutions to enable future manufacturing technologies for FPGAs requiring 0.92 mm pitch PCB designs. This paper will assess PCB vendor drill registration capability and will also evaluate PCB reliability using electrochemical migration (i.e., conductive anodic filament or CAF) and via reliability (i.e. interconnect stress testing or IST) testing. PCB manufacturing capability will be characterized as a function of back drill-to-metal gap capability. The paper will share recommendations with potential solution paths to enable PCB suppliers on fabrication of reliable 0.92 mm pitch thick PCBs (aspect ratio > 20:1) for FPGA applications.