Nickel-palladium-gold-finished terminals are susceptible to creep corrosion. Excessive creep corrosion can result in device failure due to insulation resistance loss between adjacent terminals. The mixed flowing gas test has been demonstrated to produce creep corrosion on parts with nickel-palladium-gold finished terminals. Conformal coats are often used to protect printed wiring assemblies from failure due to moisture and corrosion. However,coating may not be sufficient to protect lead terminations from failure. In this study,acrylic,silicone,urethane,parylene,and atomic layer deposit (ALD) coatings were examined for their effectiveness at preventing corrosion of nickel-palladium-gold-finished terminals. The coverage of each coating was examined,and assemblies were subjected to eight hours of mixed flowing gas as well as temperature cycling. Non-uniform coating thickness was observed in the areas of the terminals. On some areas,little to no coating material was found for the acrylic,silicone,and urethane coatings. Parylene,which had the most uniform coating,was found to provide the best resistance to corrosion,while corrosion products were observed on the terminals of inspected parts protected by the other coatings.

The iNEMI technical subcommittee on creep corrosion is developing a flowers-of-sulfur (FOS) based qualification test for creep corrosion on printed-circuit boards (PCBs). The test setup consists of a 300-mm cube chamber with two means of mounting the test specimens and flowing air over them to expose them to constant,predefined humidity and temperature conditions and sulfur and other contaminants. The FOS chamber performance has been evaluated using copper and silver foils and preliminary test runs have been conducted on PCBs from a manufacturing lot known to have failed in service. The effect of air velocity on the copper and silver corrosion rates was quite linear. The effect of humidity on copper and silver corrosion rates in the low air velocity range of less than 0.1 m/s showed a strong dependence on relative humidity. In the high velocity range of 1 m/s,there was no clear dependence of humidity on copper and silver corrosion rates. A means has been developed for applying controlled concentration of ionic contamination on selected local areas of test PCBs. Preliminary test runs have shown that ionic contamination found in fine dust may be a necessary condition for copper creep corrosion. Printed circuit boards from a manufacturing lot that suffered creep corrosion in service,with and without dust contamination applied to them,were tested in a FOS chamber at 60oC with 1 m/s air flowing over them. The PCBs with no dust contamination did not suffer creep corrosion in the 3-day test; whereas,the PCBs with dust contamination suffered creep corrosion with morphology similar to that occurring in the field.

The objective of this study is to evaluate conformal coatings for mitigation of tin whisker growth. The conformal coatings chosen for the experiment are acrylic,polyurethane and parylene. The coatings were applied in thicknesses ranging from 0.5 to 3.0 mils on 198 bright tin plated coupons with a base metal of either Copper C110 or Alloy 42. Prior to coating,light scratches were applied to a portion of the coupons,and a second fraction of the coupons were bent at 45° angles to provide sources of stress thought to be a possible initiating factor in tin whisker growth. The coupons have been subjected to an environment of 50°C with 50% relative humidity for 9.5 years. Throughout the trial period,the samples were inspected by both optical and scanning electron microscopy for tin whisker formation and penetration out of the coatings by tin whiskers. Tin whiskers were observed on each coupon included in the test,with stressed regions of the bent samples demonstrating significantly higher tin whisker densities. In addition,the Alloy 42 base metal samples showed greater tin whisker densities than the Copper C110 base metal samples. There were no observable instances of tin whisker penetration out of the coatings or tenting of the conformal coat materials for any of the non-stressed test coupons. The stressed coupons demonstrated tin whisker protrusion of the 1.0 and 2.0mil thick acrylic coating and the 1.0mil polyurethane coating for the Alloy 42 base metal samples. The greater thickness coatings did not demonstrate tenting or tin whisker protrusion. Also included in this paper are tin whisker inspection results of tin-plated braiding and wire that was exposed to an environment of 50°C with 50% relative humidity for over five years.

Embedded capacitors offer board designers the ability to address the demands of high switching speeds and high I/O count packages while stemming the proliferation of minute decoupling capacitors. Nevertheless,the incorporation into a printed circuit board of a thin dielectric layer between power and ground can introduce some unique quality and reliability challenges. Environmental stresses can degrade electrical performance over time,with sudden dielectric breakdown representing a worst case scenario. This presentation will review recent findings concerning the reliability of planar embedded capacitors,including failure modes,mechanisms and models. The emphasis will be on epoxy– BaTiO3 composite dielectrics,although other variants will be discussed.

In light of new process and product technologies in the field of embedded components,questions arise with respect to advantages and potential disadvantages to standard SMT component placement when considering reliability.
This paper is the second part in a progressively complex series of comparative analyses,testing the reliability of standard SMT components in comparison to their embedded counterparts.
In the initial round of comparative tests,we analyzed passive components. In this second part we will compare the performance of similarly specified embedded dies and standard surface mounted CSPs which are designed to simulate an active component (“dummies”) in terms of interconnectivity
The applied reliability tests shall include:
? Drop Test per JEDEC JESD22-B111: 1500g / 0.5ms
? Thermal cycle testing (TCT) per JEDEC JESD22-A104: -40°C / +125°C
? Bend Testing – Based on the IPC/JEDEC 9702 (Monotonic Bend Characterization of Board-Level Interconnects)
With these tests,as with the initial paper on embedded passives,we aim to define possible limitations,advantages,disadvantages and areas of functional application which are relevant to this direct comparison. With the addition in this study of one mechanical bend test we hope to introduce a more well-rounded picture of the reliability one should expect for different instances and component placement methodologies.
As the usage,as well as fields of application,of embedded components increases in part due to more stable and refined methods of manufacturing,it is worthwhile to examine them based on industry norms and standards as a source of comparison to traditional manufacturing methods. Part of this analysis is therefore to investigate the feasibility of employing such standards in the context of embedded components. This investigation,in turn,should offer us a holistic perspective to other current industry projects,such as the EU-funded “Hermes”.

The utilization of embedded components has increased across many applications in various industries,and with rapid emergence of technologies and the need to secure IP,new methodologies are being used to satisfy market requirements. As design teams face constant pressure to implement the latest embedded component technologies,such as embedded SoCs directly within the laminate,many workarounds are used during the design process,leading to costly errors during the manufacturing process. In this session,we will explore the various technologies and challenges with embedded components for current and future designs. We will also discuss new methods to accurately model and design using the latest embedded component technologies,how to eliminate work-arounds during the design process,and how to minimize errors in manufacturing.

The demands on volume delivery and positioning accuracy for solder paste deposits are increasing as the size and complexity of circuits continue to develop in the electronics industry. According to the iNEMI 2013 placement accuracy for these kinds of components will reach 6 sigma placement accuracy in X and Y of 30 um by 2023 [3]. This study attempts to understand the dependencies on piezo actuation pulse profile on jetting deposit quality,especially focused on positioning,satellites and shape. The correlation of deposit diameter and positioning deviation as a function of piezo actuation profile shows that positioning error for deposits increase almost monotonically with decreasing droplet volume irrespective of the piezo-actuation profile. The trends for shape and satellite levels are not as clear and demand further study.

Solder paste printing is known to be one of the most difficult processes to quality assure in electronic manufacturing. The challenge increases as the technology development moves toward a mix between large modules and small chip components on large and densely populated printed circuit boards. Having a process for quality assurance of the solder paste print is fast becoming a necessity. This article describes a method to ensure quality secured data from both solder paste printers and inspection machines in electronic assembly manufacturing. This information should be used as feedback in order to improve the solder paste printing process.

Transmission of data is a major driver in the electronics industry. Higher data volumes,high speed data transfer and short time signal transmission have to be realized to meet these requirements. To minimize losses,the Radio Frequency (RF) application and standard PCB requirements have to be realized on the same board. This additional technology puts additional demands on the PCB. To achieve these targets,the material,build up and design need to be adjusted to both requirements. Test procedures,focused on particular RF properties have to be considered as well.
This paper examines the development of mixed Microwave and Digital Multilayer printed circuit boards (PCB) for high density application. The major innovations include Radio Frequency (RF) functions,coupled with stacked copper filled Microvia and High Density Interconnection (HDI) technologies,made together into one multilayer construction.
The aim of this study shows the development and validation of raw materials to meet dielectric,power and signal loss properties. From a manufacturing point of view,asymmetrical build up of raw materials with specific RF properties and other PCB raw materials will be investigated,to demonstrate the compatibility of mixed materials in a multilayer PCB´s.
This research was carried out by the company in cooperation with MIDIMU,a European Consortium Project.

Cavity technology in a Printed Circuit Board (PCB) has existed for many years. The methodology to create the cavity in the PCB has evolved over time as technologies have advanced and the manufacturing process varies by the individual PCB fabricator as well as the reasons for using the cavity technology. For the purpose of this paper,a cavity will be defined as a hole in the PCB going from the outer copper layer to an inner copper layer,but not completely through the PCB. The cavity design and assembly issues identified during the design of experiments (DOEs),the findings,reliability results,and conclusions will be discussed in this paper.