The number one issue identified by the 2009 International Electronics Manufacturing Initiative (iNEMI) Boundary-Scan survey was problems with obtaining correct and compliant boundary-scan description language (.bsdl) files from the semiconductor industry for use in boundary-scan printed circuit board assembly (PCBA) test generation. The major conclusions from the survey were:
•The semiconductor industry needs to make a greater effort to produce correct and compliant BSDLs.
•A better job needs to be done verifying .bsdl file compliance to the implemented JTAG hardware.
Non-compliance is typically found when a test is generated and it doesn’t work! The consequences of not having correct and compliant .bsdl files to generate boundary-scan tests is the inability to generate boundary-scan based tests and if tests cannot be generated,the result is lower overall test coverage for PCBAs which results in higher manufacturing costs and lower overall product quality. The work presented here by the iNEMI Boundary Scan Phase 3: Investigation into Challenges of Using .BSDL Files project group takes a more comprehensive view of the problem by surveying the industry to determine if issues associated with .bsdl files identified in the 2009 iNEMI Boundary-Scan survey still exist (and if so to what extent) and to identify new issues.

As device density continues to maximize the PCB real estate the reflowing of neighboring components or damaging of heat-sensitive components in the rework process continues to cause problems. Devices either have to be removed,thereby reducing rework throughput,or devices get damaged during the reflow process if not shielded from the heat generated during rework. The shielding solutions used most commonly either cannot be delivered in a timely fashion or offer very limited protection to these heat sensitive devices. A new,flexible heat shielding solution is now available that can be easily modified by the users and is inexpensive enough to have on hand. Most importantly it is an effective way to reduce the temperature on nearby components during the reflow/rework process so that neighboring devices do not go into reflow. This study documents the relative effectiveness of this ceramic nonwoven material as well as different shielding materials in protecting neighboring components during PCB rework.

In the rework environment,most equipment and procedures are designed for low volume repair/rework process. When a high volume rework is needed,the challenges begin. For example,a long cycle time is required to perform ball grid array (BGA) rework. When we need to remove material,do pad dressing,pad inspection,paste printing and place a new BGA,those steps increase the amount of dedicated rework equipment. Some machines are used to remove material,others are used to do pad dressing and others to place a new BGA. This results in hundreds of rework tools and equipment on the production floor. That volume of rework consumes enormous amounts of resources,requiring process controls such as daily profiling and maintenance using excessive hours of human resources. In addition,the standard rework process has low yield and high scrap rates. The Selective Reflow Rework Process is an approach to improving the high volume rework process,increasing process capabilities and process repeatability by using a standard reflow oven of 12 zones,pick and place machinery,semi-automated printing gear and Solder Paste Inspection (SPI) implementations. This approach was able to reduce the amount of rework equipment by more than half. Our human resource requirements (indirect and direct labor) were cut by more than 50% and our rolled throughput yield increased from 68.9% to 84.14%. The Selective Reflow Rework Process is less reliant upon operators and has become a repeatable,stable rework process. To obtain this advantage and have a successful implementation of this technology,the process requires new controls for printing,and check points before proceeding to the next process step. The printing process has a major impact on the HiP reduction,optimizing solder paste transfer efficiency (TE) and establishing a real SPC that gives real time warnings of anomalies. By identifying challenging process key parameters,including paste height,printing technique,pallets design and thermal barrier protection of TH parts,this paper will discuss some aspects of the process optimization and changes made to improve the quality of the rework process.

The biggest problem with designing rigid-flex hybrid PCBs is making sure everything will fold in the right way,while maintaining good flex-circuit stability and lifespan. The next big problem to solve is the conveyance of the design to a fabricator who will clearly understand the design intent and therefore produce exactly what the designer/engineer intended. Rigid-Flex circuit boards require additional cutting and lamination stages,and more exotic materials in manufacturing and therefore the cost of re-spins and failures are very much higher than traditional rigid boards. To reduce the risk and costs associated with rigid-flex design and prototyping,it is desirable to model the flexible parts of the circuit in 3D CAD to ensure correct form and fit. In addition it is necessary to provide absolutely clear documentation for manufacturing to the fabrication and assembly houses. The traditional attempt most design teams use to mitigate these risks is to create a "paper doll" of the PCB,by printing out a 1:1 representation of the board and then folding it up to fit a sample enclosure. This has a number of issues: 1) The paper doll does not also model the 3D thickness of the rigid and flex sections. 2) The paper doll does not include 3D models of the electronic components mounted on the PCB. 3) This approach requires a physical sample of the final enclosure which may not yet be final in its design either. 4) If the mechanical enclosure is custom designed,a costly 3D print will be required for testing. This adds much time and expense to the project. As cool as 3D printers are,it's not a sensible use for them if the modeling can be done entirely in software. This paper discusses practical steps in two approaches to solve these problems,contrasting against the traditional "paper doll" approach above. In the first scenario,a 3D MCAD model of the PCB assembly can be created in the MCAD package where a "sheet metal" model can be generated for the PCB substrate model. This sheet metal model can be bent into shape in the MCAD software to fit the final enclosure and check for clearance violations. This is not the best approach but it is better than paper dolls. In the second scenario,a significant part of the enclosure or mechanical assembly model is brought from the MCAD package into the PCB design software,where the rigid-flex board outline can be designed specifically to fit with it. Rigid-flex layer stack sections can be defined and then flexible circuit areas have bending lines added. In the PCB design tool's 3D mode,the folds are then implemented to reveal where potential clearance violations and interference occurs. The PCB design can then be interactively modified to resolve the problems and check right away - without having to build any further mock-ups or translate design databases from one tool to another.

Sustainable product design and the task of bringing new,earth friendly products to market is a top priority for corporate leaders in the manufacturing industry. By not reaching their compliance and sustainability goals,manufacturers risk loss of market share,fines for non-compliance against regulatory directives and possible damage to their brand. Managing material disclosure information from the supply chain is one of their biggest challenges. On average,80% of manufactured products today are comprised of components sourced from suppliers. This means that if the manufacturer’s goal is to understand how sustainable or compliant their product is,they must first pull all of the supplied parts into the product picture before doing any type of sustainability or regulatory analysis. This is no small task,especially for manufacturers dealing with 100s to 1000s of suppliers and supplier parts within a deep multi-level supply chain. The increased need to sell products in global markets,where a large portion of the product contains components sourced from around the world,coupled with the trend for higher product complexity adds another layer of challenges to manufacturers in trying to gain holistic views of their products in order to check for compliance against regulatory and industry directives. The most complex and tedious part of compliance and sustainability is getting accurate and complete data from suppliers. Manufacturers will need to focus on supplier interaction and automation of that process using a multi-faceted and “best-practice” approach,which could include functions such as: email interaction,web portals,integration to on-line databases,engaging third party data collection agencies,general PLM framework capabilities to exchange different document types,support for industry standards and full material disclosure from suppliers. Using an enterprise PLM framework to automate the process of gathering and managing supplier disclosure data,manufacturers will not only benefit today in addressing current sustainability challenges and gaining a competitive edge,but also tomorrow in addressing future needs and requirements to produce earth friendly,innovative and compliant products.

•Introduction to printed and wearable electronics
•Flexibility testing challenges
•Proposals for flexibility testing
•Validation case studies
•Future work

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PCB assembly designs become more complex year-on-year,yet early-stage form/fit compliance verification of all designed-in components to the intended manufacturing processes remains a challenge. So long as librarians at the design and manufacturing levels continue to maintain their own local standards for component representation,there is no common representation in the design-to-manufacturing phase of the product lifecycle that can provide the basis for transfer of manufacturing process rules to the design level. A comprehensive methodology must be implemented for all component types,not just the minority which happen to conform to formal packaging standards,to successfully left-shift assembly and test DFM analysis to the design level and thus compress NPI cycle times. The elements of such a solution include implementing de-facto standards for package and pin-type classifications,as well as DFM analysis rules that are associated with these classifications and the intended manufacturing processes. The resulting solution enables the transfer of DFM rules from the manufacturing process expert to the design and NPI engineers on the design side responsible for verifying manufacturing-process compliance of new product designs. This paper will demonstrate the technological components of the working solution: the logic for deriving repeatable and standardized package and pin classifications from a common source of component physical-model content,the method for associating DFA and DFT rules to those classifications,and the transfer of those rules to separate DFM and NPI analysis tools elsewhere in the design-through-manufacturing chain resulting in a consistent DFM process across multiple design and manufacturing organizations. Following establishment of a common source of component definitions and classifications,rules-based generation of assembly-level machine libraries is enabled from the same source that drove the DFM process,resulting in right-first-time launch of a new product into the manufacturing process.

The miniaturization of electronic devices demands the continued shrinking of system z-height. A significant consequence of these ultra-thin systems is yield loss due to high temperature warpage during SMT reflow. This warpage results from the Coefficient of Thermal Expansion (CTE) mismatch between the key materials,such as Si,organic substrates,and Cu in the SoC-to-PCB system stackup. Warpage impacts the solder joint formation,and can result in both bridging and open defects due to the compressive and expansive forces experienced during solder joint collapse at high temperatures. Solutions typically consist of mechanical reinforcement such as molding compounds or metal stiffeners applied to the substrate,and while successful,these solutions can be expensive. In this study,we investigate the impact of temperature on the system warpage profile and find that reducing the reflow peak temperature from 245C to <180C appreciably reduces the amount of warpage,thus improving SMT yields. To reduce the reflow temperature,we have used Bi-Sn-Ag solder alloys with a M.P. of 138C. Although reduced reflow temperature improves SMT yield,Bi containing solders have been previously shown to induce brittleness [1] that can jeopardize joint reliability. To overcome this,we further investigate a class of Bi-based solders that also contain epoxy resins to mechanically reinforce the solder joint. This paper describes the yield improvements and defect mechanisms as a function of temperature as well as the impact of epoxy based solder reinforcement materials on SMT process yields. Lower reflow temperatures bring added environmental benefits and we have conducted an analysis of the potential energy and cost savings in HVM due to lowering reflow temperatures by 65C-80C.

Sn3.0Ag0.5Cu (SAC305) is currently the most popular near eutectic lead-free alloy used in the manufacturing processes. Over the last several years,the price of silver has dramatically increased driving a desire for lower silver alloy alternatives. As a result,there is a significant increase in the number of alternative low/no silver lead-free solder alloys available in the industry recently. Our previous study showed that many alternative low silver solder paste materials had good printing and wetting performance as compared to SAC305 solder pastes. However,there is lack of information on the reliability of alternative alloy solder joints assembled using alternative low silver alloy solder pastes. In this paper,we will present the reliability study of lead-free solder joints reflowed using various lead-free alloy solder pastes after thermal cycling test (3000 cycles,0°C to 100°C). Six different lead-free pastes were investigated. SAC305 solder joints were used as the control. Low and no silver solder pastes and a low temperature SnBiAg solder pastes were also included.