With increasing popularity and momentum for wearable and printed electronics,stretchable printed ink has become a hot subject for study and application. Circuitry printed from stretchable ink remains conductive even when it is elongated at a high percentage,thus it is useful for many wearable applications where stretching is required. There have been limited studies on stretchable ink and its stretchability. The characteristics of the stretchable ink and how different factors impact its stretchability are not well studied and therefore unknown. To accommodate the increasing demand for wearable applications,it is necessary to perform evaluations on the stretchable ink. This paper presents the company studies on stretchable printed ink. A test coupon is designed to prevent instability of connection between test probe and printed ink pad. Different design and test parameters are evaluated to shed light on how they affect the stretchability. The study is very useful to not only optimize the ink stretchability,but also provide insight on how to improve ink chemistry to enable more stretchability.

The rules of the game in PCB production are changing with new disruptive technologies. At the company there has been the implementation of a “primary image inkjet-resist” printer for both inner-layer print and etch and outer layer pattern plating processes in full production. Inkjet printing has become a crucial building block for the first zero emission,fully automated PCB factory. Ink jetting resist eliminates standard lithography processes while still providing a fully digital solution in a very small footprint. This technology combined with an intelligent nozzle conditioning routine,and real-time ink channel acoustic monitoring with double channel redundancy,gives full process control during production. To ensure higher yields and continuous feedback,the print is also fully inline scanned by integrated AOI at full process speed to check the print result before etching (Image Quality Inspection). The fully automated panel logistics,the clean machine,and reduction of processes enables CAM to etch processing within minutes. The short overall process pipe line and digital imaging gives flexibility to the flow and facilitates easy mixing of jobs. With “jet-resist”,production becomes a straight forward process,greatly reducing process steps and complexity compared to traditional production. Furthermore,since the resist is based upon a hot melt wax,the use of next generation etching and stripping process techniques have been employed that have resulted in 100% closed loop rinsing,stripping,and etching processes that consume no chemicals,and require no waste treatment whatsoever. The only by-products are solid resist and pure copper metal,which may be reused in the copper plater. Additionally,the precision of the ink placement on the substrate,further allows for a 5-10% increase in panel utilization compared with standard dry film and liquid resist application processes. The overall solution represents the next generation in PCB Fabrication,and a formula for manufacturing in North America and Europe at equal to or lower cost than current Asia-Pacific sources,in much shorter cycle times.

From photo film to digital camera,from letters to emails,from books to e-readers,from vinyl to MP3: the whole world is turning digital. Yet,ironically,the core compound driving the digitization of technologies and products is still being produced using analogue technology. Indeed,printed circuit boards (PCBs) are the beating heart of all digital “alternatives”,but the vast majority of PCBs are still produced using rotogravure print rolls,dry film or coated resists and phototool films. However,digital technology has become available to replace analogue imaging technology: inkjet printing is the digital alternative to the phototooling film process. Even though inkjet printing started off in merely marking/coding and document printing,it grew industrial in wide-format and billboard printing and is now mature enough for implementation in industrial production processes. The market of digital industrial product decoration is growing as we speak. Along with this,inkjet tools have been created for real high end industrial production. Inkjet technology based on UV-curable inks is especially ready for real production implementation. Besides the relatively well-known and readily adopted inks for legend printing on PCBs,UV-curable inkjet inks that are resistant to acidic etching and that can be stripped off in regular PCB production chemicals are now also available. The benefits of digital printing using these UV-curable etch resistant inks are clear and very relevant to PCB production: no time-consuming film production,no film exposure step,no development. With ink jet printing the images are generated on the fly and thus allow dynamic imaging. Since digital printing is an additive process,fewer raw materials are used,causing less waste. These UV curable inks are caustic strippable inks and are thus drop-in for present etch and strip lines. In this paper,the unique position of inkjet printing in PCB production will be highlighted and the chemical technology behind the inks will be explained in detail.

This experiment considers the reliability of a variety of different electronic components under isothermal aging and subsequent thermal cycling (TC) testing. The components are evaluated on 0.200” power computing printed circuit boards with OSP and a several different solder alloys. Single-sided assemblies were built separately for the Top-side and Bottom-side of the boards. This data is for boards on the FR4-06 substrate. Isothermal storage at high temperature was used to accelerate the aging of the assemblies. Aging Temperatures were25oC,50oC,and 75oC. Data from aging times of 0-Months (No Aging,baseline),12-Months,and 24-Monthswill be presented. Following isothermal aging,the assemblies were subjected to thermal cycles of -40°C to +125°C on a 120 minute thermal profile. The test was subject to JEDEC JESD22-A104-B standard high and low temperature test in a single-zone environmental chamber to assess the solder joint performance. The principal test components are 5 mm,6mm,13mm,15mm,17mm,31mm,35mm and 45 mm ball grid array (BGA) packages with solder ball pitch varying from 0.4 mm to 1.27 mm. Most of the BGA packages are plastic over-molded,while the 31mm and 45mm packages are Super-BGAs (SBGAs). Several surface mount resistors (SMRs) are also considered in order to understand the effect of solder paste composition on paste-only packages. The primary solder for package attachment in this experiment is standard SAC305,with SnPb eutectic comparison/baseline. Two alternative solders designed for high-temperature reliability are also considered.

The July 2006 implementation of ROHS exempted automotive applications from converting to lead free technology. Nine years later,all major OEM and Tier 1 automotive manufacturers have converted or are in the process of converting to lead free circuit assembly processing. Starting with SAC (SnAgCu) alloys as a baseline for lead free soldering,in the last years several specific alloys were developed in order to improve resistance to high temperature creep,vibration survival and the ability to withstand thermal cycling and thermal shock. The paper compares three different solder alloys and two flux chemistries in terms of void formation and mechanical / thermal fatigue properties. Void content and reliability data of the alloys will be presented and discussed in relation to the acceptance criteria of a Tier 1 /OEM automotive supplier. As a result,a ranking list will be presented considering the combined performance of the alloys. In order to analyze the void formation and mechanical behavior of different solder alloys and flux chemistry combinations,statistical methods are used.

IPC J-STD-001Fand IPC-A-610F require a minimum Heel Fillet Height (F) for Flat Gull Wing Leads of solder thickness (G) plus lead thickness (T) for Class 3 products.[1]It is shown in this work that this requirement prevents a solder joint geometry from being optimized for reliability especially under temperature cycling. Therefore,a reconsideration of the Class 3 criterion is proposed in this work. Temperature cycling tests in combination with finite element (FE) modeling have shown that there is an optimal solder volume to achieve optimum TCoB (temperature cycling on board) performance. On the one hand,increasing the solder volume beyond this optimum results in considerably more solder wetting of the pin shaft and thereby induces a stiffening effect on the gull wing lead. This effect results in higher stresses in the critical cross section area of the solder joint and thereby leads to a reduced solder joint lifetime in temperature cycling. On the other hand,reducing the solder volume results in a (too) small connection area and thereby reduces the solder joint lifetime. Balancing these two counteracting effects of solder volume on TCoB performance enables optimum product reliability. The current IPC Class 3 criterion in combination with process tolerances requires a nominal solder volume in design that is above the described optimum. Therefore a reduction of the minimum heel fillet height is proposed to enable a robust and optimum solder joint reliability for future products. It can be shown that the proposed change in solder joint design has a positive effect on product reliability concerning different loading conditions and failure modes as well.

The world of electronics continues to increase functional densities on products. Many of the miniaturization technologies were developed for the consumer market with the smart phone specifically. Many designers in other areas such as infrastructure,medical,power,telecom,and other industries also desire to use similar components and are also looking at ways to miniaturize the product or increase the functional density. This paper will explore some of the common miniaturization technologies and their application to larger form factor boards. Items such as 01005/0201 components,fine pitch CSP/QFN,component to component spacing,and package on package components will be explored through this paper. Key items will be highlighted that will help designers and assemblers understand the advantages and disadvantages of using these various techniques on various board types. Items that are “easy” for a cell phone board may not be as easy on a network infrastructure board. There are many more components and items that need to be thought through and evaluated to determine if these miniaturization technologies are applicable.

To keep up with shrinking system volume requirements for the Internet of Things and wearable devices while maintaining maximum device functionality requires an integrated approach to SoC and SiP optimization. To accomplish this we investigated the Direct Chip Attach (DCA) of a high density WLCSP onto the Printed Circuit Board (PCB) to obtain the smallest system footprint possible without compromising performance. Typically,to keep costs low,SoCs do not support the most aggressive interconnect density,and instead use wire-bond or large pitch flip chip packages to mount to the board. In this study,we take the opposite approach. Using DCA to attach the SoC directly to the PCB,we maximize the interconnect density between the board and silicon while keeping the cost low by eliminating the SoC package. This paper describes the impact of attaching a high performance SoC directly onto the board in terms of the PCB design,PCB fabrication and cost. We also investigate the SMT challenges of mounting the silicon directly onto the PCB at a 260 µm pitch array. Key metrics in this study include SMT yield,PCB routing,and PCB fabrication constraints as they relate to signal quality. In addition,the paper discusses future development challenges that face both the designers and PCB manufactures as they progress to support larger and denser direct chip attach products.

Modern consumer electronics are driving the adoption of smaller featured SMT devices such as 0.4 mm or smaller pitch CSP,and 01005’’ / 0402 metric discrete devices. Already roadmaps have been suggested to explore the use of smaller pitch CSP and 03015discrete devices,which are only around 64% the size of 01005 devices. On their own these challenges can be met by using stencils with thinner materials allowing sufficient area ratios to maintain the established safe area ratio guideline of 0.6% or higher. However when having to process fine feature devices along with larger devices such as connectors and RF shields,which usually require higher paste volumes to overcome co-planarity issues,the area ratio factors encountered in real production are dropping significantly below the conventional rule of thumb of area ratios having to be above 0.6 and in some instances below 0.5 area ratios. With this forced compromise in area ratio guidelines comes a compromise in process window robustness and subsequent print and even placement process quality. In order to try and redress this issue,different technologies have emerged in stencil materials and treatments combined with the use of finer grades of solder paste,but the question remains: “In isolation or by adopting a combination of these technologies is it enough,to establish a robust 03015 process?” This paper will review major steps considered and taken for the development of a robust 03015 process which was successfully Demonstrated at the company in-house show during Productronica in November 2013,and it will focus on the activities for the solder paste print process

This paper examines the use of Light Interferometry and the relevant parameters used to measure copper surface roughness before and after oxide alternative. Also discussed are the limitations and drawbacks of some of the traditional measurement parameters as they apply to copper surface roughness for conductor loss and signal integrity characterization and process control. In the PCB industry,we have seen minimal industry wide agreement on both the terminology,equipment and measurement parameter standards for the different foil types available from the copper foil and laminate suppliers. In the last 5 years,studies have indicated that high copper surface roughness is a significant factor in increased conductor losses. Specifically,the very high roughness of “Reverse Treat Foil” or “Standard Foil” whether used on the resist side or on the inner layer side was of greater significance than the micro roughness added by the oxide alternative bonding promotion treatment on the resist side.1Since then,the copper foil suppliers had focused on supplying copper foils with significantly reduced roughness on both sides of the foil in order to reduce high speed signal loss and preserve Signal Integrity. The traditional “Reverse Treat” or “Double Treat” foil typically has RSAR (Roughness Surface Area Ratio) of 1.0 to 1.2,Ra of 0.7 to 0.8 microns and Rz of 8-10 microns on one or both sides of the foil. “Standard” foil typically has similar roughness on the inner layer side and RSAR of 0.3 to 0.4,Ra of 0.3 to 0.4 microns and Rz of 3-4 microns with the smooth foil on the resist side. Now we are seeing VLP (Very Low Profile) with Rz 3-4 microns and HVLP (Hyper Very Low Profile) copper foils with 2-3 microns Rz on both sides. Concurrently,we have been exploring the measurement of the “resist side” copper surface micro roughness following oxide alternative process,or bonding promotion treatment,to better understand its role in Signal Integrity and establish in-process control measurement capability.