Since the beginning of the digital printing era,methods have been sought to employ this knowledge for use in an elegant approach for producing circuitry. As long ago as the early 80s,companies were working with inkjet printing to apply a
conductive or catalytic ink to standard circuit substrates in the quest to build an additively printed circuit. In 1983,I visited a small Silicon Valley startup company,Elf Technology,with Joe Fjelstad. In this small office park,Joe had taken a standard desktop inkjet printer and developed an ink with high enough conductivity to support electroplating. He was able to go from CAM file to inner layer on a desktop followed by electrolytic plating. Unfortunately,the technology
never made an impact on the market. In the mid 1990s,while working at Litchfield Precision Components (now Innovex),I was involved in a development project with a spin off of Bayer AG called AMEG. This small engineering company had developed a UV curable ink that was catalytic to electroless copper and could be photoimaged. We discussed inkjet application at the time,but the project stalled because of continuing problems with the stability of the ink bath.
With advances in both inkjet head technology and ink formulations,the pursuit of this ultimate “printed” circuit has advanced to the point that in 2007 we should see an impact in the market.

Increased electronic functionality can be achieved through the development of more complex silicon integration but that course generally requires a great deal of capital resources and an excessive amount of time. Hand-held communication and entertainment products necessitate a very short development cycle. And,with each generation offering more and more features and/or capability,rapid deployment of system level integration and miniaturization becomes a priority. In addition,the end user is expecting that each generation of product to be smaller and lighter that its predecessor. Companies are finding that for these rapidly evolving products,the multiple-die package concepts are proving superior to the system-on-chip alternative because it minimizes financial risk and has the potential for economically integrating several different but complementary functions. The paper developed for the IPC APEX program presents a view of current expectations for multiple-die BGA and CSP technology for wireless applications and review the evolution taking place in developing systemin-
package capability.

This paper presents the results of our study on the development and optimization of lead-free wave soldering process for large and thick printed circuit boards (PCB),through multiple designs of experiments (DOEs) including many variables from design,material,component and process. Design variables were pin-to-hole ratio,pad diameter,annular ring diameter,component orientation,spacing,thermal relief pattern,internal copper thickness,and the number of copper layers connected to PTH barrel. Material and process variables included flux materials,flux amount,preheat temperature,solder pot temperature,conveyor speed,contact time,wave atmosphere and wave system. A variety of plated through hole (PTH) components were tested. Two board thicknesses (2.4mm and 5.0mm) and two board surface finishes (immersion silver and immersion gold) were used. The results showed that there were strong correlations between flux materials,process conditions and hole-fill. Bridging and insufficient solder defects were reduced by optimizing wave process parameters. Design parameter optimization could be used to improve the PTH hole-fill,and reduce defects of PTH bridging,insufficient solder on SMT components,and voiding in the PTH solder joint.

fast approaching this horizon is the 0.3mm CSP. This device represents a major assembly revolution within the Surface mount assembly (SMT) arena. The implementation of this device will require arrays of mass imaged solder paste that only a few years ago where within the hemisphere of semiconductor fabrication. This transition into SMT is a huge step when you consider the typical sub 7 sec cycle times requirements of SMT against relatively slow Semicon ball bumping cycle times,the thin uneven FR4 boards generally used in SMT against the perfectly flat wafers found in Semicon and the standard working environments opposed to the clean room environments found in Semicon.
This paper will research the key elements that influence the deposition process. Process design factors such as solder paste,squeegee construction and stencil design will be fully investigated. In addition the impact of typical fabrication defects associated to the fabrication of stencils will be observed to ensure that an authentic picture is created and not one that belongs in a laboratory. The deliverables from this paper will be clear and concise implementation solutions for the surface mount engineers who are about to encounter the 0.3mm C.S.P.

The consumer’s interest for smaller,lighter and higher performance electronics products has increased the use of ultra fine pitch packages,such as Flip Chips and Chip Scale Packages,in printed circuit board (PCB) assembly. The assembly
processes for these ultra fine pitch packages are extremely complex and each step in the assembly process influences the ssembly yield and reliability.
Generally speaking,end-of-line SMT defects can be greatly influenced by the stencil printing operation. The importance of the stencil printing process progressively increases as the pitch and the package size decreases. A thorough understanding of basic stencil printing principles would facilitate the design of printers,stencils and pastes,and would ultimately permit the extension of reliable print techniques to the ultra fine print arena.
Stencil design and stencil fabrication techniques are critical factors that affect the stencil printing process. This work compares the stencil design elements,such as aperture wall taper and aperture wall finish that play a major role in the print
performance of the small apertures. Designed experiments are performed to determine the ‘optimum’ level of aperture taper and aperture wall finish. The study also compares three major stencil-manufacturing techniques (chemical etching,laser cutting and electroforming) for small aperture printing. From the knowledge gathered,guidelines are being developed for the stencil design and the stencil printing process for small apertures.

Stencil design is one of the key factors in determining how well any particular stencil will print solder paste. Today’s high volume,24 hour a day,seven days a week manufacturing operations require stencils that will reliably and repeatably print solder paste with minimum stencil wiping required.
The area ratio of the stencil apertures is a primary factor in determining how well any particular stencil will print solder paste. Area ratio is the ratio between the area of the stencil aperture and the area of the aperture walls. Until the last few years the only stencil design calculation that was required was aspect ratio. Aspect ratio is the ratio between the width of the aperture and the thickness of the stencil. Aspect ratio was an excellent predictor of how well a stencil would print solder paste. However,as smaller and smaller component packages have been introduced into electronic products,smaller stencil apertures have been required. The smaller apertures now have opening areas that are very close to if not smaller than the area of the walls of that aperture. Since there are two competing forces for the solder paste,the force attempting to hold the solder paste in the aperture and the force attempting to pull the solder paste out of the aperture,area ratio is now the key factor in determining how well a stencil will print solder paste. The higher the area ratio the higher transfer efficiency of the solder paste. Transfer efficiency is a calculation of the percentage of solder paste printed into the aperture that is printed onto the printed circuit board pad.)
The area ratio rule identifies an area ratio of 0.66 or higher to produce a stencil that will print solder paste well. Many experiments by Speedline Technologies and others have confirmed the minimum 0.66-area ratio requirement. The 0.66 area ratio requirement experiments were conducted using solder paste with type 3 solder powder size. This paper will discuss experiments that have been conducted by Speedline Technologies and Indium Corporation to determine if a lower area ratio can be used when using solder paste with type 4 and type 5-powder size. If a lower area ratio can be identified for solder paste using type 4 and/or type 5 solder paste,electronic manufacturing operations will have another option in designing stencil for products using miniature components such as 0201 and 01005 resistors and capacitors.

Mechanically drilled through holes in PWBs form interconnects between copper layers through the use of copper pads. These pads are larger than the drill diameter to account for such factors as layer-to-layer misregistration during lamination,drill misregistration,and drill wander. The requirements for the pad’s remaining annular ring after drilling are specified in IPC-6012,Qualification and Performance Specification for Rigid Printed Boards. For Performance Class 3 (High Reliability Electronic Products),these requirements are 0.001” minimum annular ring for internal layers,and 0.002” for external layers.
Performance Classes 2 and 1 allow 90º and 180º breakout of the hole from the pad,respectively. This leads to the conclusion that breakout or tangency of the hole to the pad are less reliable than complete annular rings. Testing was performed to determine the reliability of plated through holes that met Class 2 requirements compared to holes that met Class 3 requirements. Interconnect Stress Testing (IST) coupons were used as test vehicles,with drill location offsets
applied to some coupons to force tangency or breakout (Class 2). In addition,two pad sizes were used,one representing standard density designs (larger pads) and the other representing higher density designs (smaller pads). Results from IST showed that the higher density design practice had equivalent or higher reliability,even with tangency/breakout. Finite Element Analysis (FEA) is used to validate these results.

The migration to lead free reflow is bringing many challenges for the PCB industry. High Tg laminates,stability of materials thru 2X reflows,rework,moisture sensitivity etc. This requires careful evaluation of new laminate materials,balancing component layout and optimization of reflow profiles to minimize damage to PWBs. This is critical for thin PWBs (less than 0.1 mm) boards used in cell phones and other portable products that use build up microvia technologies.
The trends of increased functionality and reduced size of portable wireless products,such as handsets; PDAs are demanding increased routing densities for printed circuit boards. The handheld wireless product market place demands products that are small,thin,low-cost and lightweight and improved user interfaces. In addition,the convergence of handheld wireless phones with palmtop computers and Internet appliances is accelerating the need for functional circuits designed with smallest,lowcost technology.
Historically,the industry has met this challenge through high density interconnect technology and increased silicon integration and component miniaturization. Microvia high density interconnect (HDI) also known as build up technology,is one method for constructing circuit boards with high routing density demands. [1].
For HDI board,vias can be formed using unreinforced dielectric such as Resin Coated Foil (RCF),using processing techniques such as laser drilling or photoimaging. The vias are then metallized using electroless copper/electrolytic plating. The advantage of the HDI construction is the ability to create smaller vias (6 mils) and via pad sizes. This enables higher routing density,lower metal count,reduced board area and increased functionality as compared to conventional boards. HDI improves the wiring density by using build up microvias in the outer layers. However there is still dead space where components cannot be mounted and lines cannot be wired,because of staggered via hole structure.
On the other hand,ALIVH-G (Any Layer Interstitial via Hole) needs no through hole. This is because any two layers are electrically connected by IVH (Interstitial Via Hole). The IVH can be placed in any position. Since there is no through hole
that disturbs interconnections between components,the dead space becomes reduced and the wiring capability is improved greatly. [2]
Past board technologies used stacked microvias on the outer layers. Current board designs use ALIVH-G technology. These vias are laser drilled and the interconnection technology used is conductive copper paste. The typical design rule is Lines/Space 100/100 micron and Via/Land is 200/400 microns. ALIVH-G technology makes a lightweight substrate (less than 100g). The paper presents the evaluation conducted to ensure the stability of the laminate and microvias through the double-sided lead free reflow process. This was evaluated as a part of the phone product qualification.

The continued fast pace towards miniaturization is leading circuit board designers to push the envelope on integration density. This trend is driving fabricators to closely look at methods and processes that will enable the move towards sequential lamination and blind and buried via technology. Circuit board fabricators particularly in North America are adopting techniques such as via filling capability with non-conductive,high Tg,low CTE plugging pastes. This paper describes the implementation of the via filling process in a highly effective and reliable fashion for high density,high aspect ratio printed wiring boards. Close attention is paid to use of these via filling materials under high temperature assembly conditions. In addition,via plugging material requirements,equipment considerations and process limitations will be presented. Further,the pros and cons of different filling techniques are discussed. Finally,desmear and metallization techniques to insure adhesion of the plating to the filled via are presented in the context of “Best Practices.”

Tin whiskers are needle-like crystals of tin growing from pure tin or high-tin alloy surfaces,which may grow long enough to cause electrical shorts. Conformal coatings provide some protection against these shorts,partly by suppressing or slowing whisker growth,but primarily by deflecting or buckling a whisker growing from an opposing surface. The longer an unsupported cantilevered whisker,the more likely it is to bend or deflect. This paper addresses the capability of a whisker to penetrate an adjacent coating,and does not consider the effect of a coating on the propensity for whisker growth. In the present work,an analysis was conducted to determine the critical spacing between coated conductors below which a whisker is likely to penetrate the conformal coating on the adjacent conductor and cause a short. The analysis is based on the critical
buckling force of an angled whisker using two different boundary conditions: fixed at one end where the whisker slides along the coating surface,or fixed at one end and hinged at the other,where friction prevents the whisker from sliding. By using the critical compressive strength of the coating (derived from Durometer measurement) and the area of the whisker tip,the critical force needed to penetrate the coating is determined and compared to the tin whisker buckling force. The computed compressive force that is required for the whisker to penetrate the coating can be considerably less than if the coating is
assumed to behave elastically. By solving the buckling relationship for whisker length at various whisker angles,the minimum coated-conductor spacing is determined as a function of whisker angle. Then,by comparing the computed
spacing-angle relationship with published data on the distribution of whisker angles,the minimum expected (mean) coating gap can be determined,in addition to the absolute minimum gap. Based on this analysis,whisker re-penetration is unlikely for components with lead pitch of 1.27-mm and above,though risk is higher for fine-pitch components with some “soft” coatings.