Surface Insulation Resistance (SIR) testing is a standard method used to characterize soldering and cleaning processes that result in acceptable levels of flux and other residues. Several different materials are used to assemble printed circuit cards. Residues can be present on the assembly from solder flux, solder paste, solder wire, underfill materials, adhesives, staking compounds, temporary masking materials, cleaning solvents, conformal coatings and more. Miniaturization of components increases risk due to tighter pitch, low standoff gaps, and residues trapped under the component termination.

In recent years, analysis of residues and their effects has shifted from a global examination of ionic residues (i.e. the entire assembly) to a more site-specific examination of spot or local contamination. The majority of an assembly surface may have acceptable levels of residues, with problem areas confined to a few components. Therefore, it was the desire to advance the state of the art in SIR testing and design cost-efficient test components and test vehicles that would allow an assembler to examine these problem point-sources of contamination. The goal of this research study was to design and evaluate an economical test board and laminate based components which mimic challenging components, and compare them to an accepted industry standard assembly, the IPC-B-52 standard test assembly.

A series of flux systems have been developed which would result in a reduced viscosity after reflow. This enables a high viscosity, high tack flux to be used to secure components at the component placement and reflow stage but ends up with a low viscosity flux residue after reflow, thus facilitating the flux residue to be cleaned. A technique for forming such special fluxes is to establish a temporary association force within the materials themselves, such as an acid-base association. This kind of association force can increase the apparent molecular weight and cause material viscosity to increase. After a heating process, one of the critical ingredients was evaporated, thus eliminating the association force, causing a decrease in the apparent molecular weight, and consequently a decrease in viscosity or an increase in mobility. The evaporation of one ingredient can be the result of one ingredient having a lower boiling point, or the decomposition of one ingredient during heating. A strong association force is desired to allow this acid-base combination approach to work. In this work, the volatile ingredient approach was less effective than a decomposable ingredient approach, presumably due to the formation of a bigger association cluster from the decomposable ingredient.

KEYWORDS Flux, viscosity decrease, reflow, clean, SIP, flip-chip

Certain high-reliability pockets of the electronics industry, such as telecommunications, defense, aerospace, and medical, often put great weight on the cleanliness of the finished PCBA. There are a few reasons why this cleanliness is deemed important, ranging from facilitating conformal coating adhesion, to cosmetics, to reliability. Years ago, PCBAs in these industry segments were often assembled with RMA classified solder pastes and fluxes and then cleaned to remove the flux residue. Many things have changed over the years, including the evolution of RMA solder pastes and fluxes into rosin-based no-clean solder pastes and fluxes, which are identified with a J-STD-004 classification of ROL0 or ROL1. The number of truly RMA classified soldering products has dropped dramatically, forcing many longtime RMA users to convert to modern rosin-based no-clean solder pastes and fluxes. For many of these converted applications, the legacy of cleaning for the sake of flux residue removal lives on for many of the same reasons that caused PCBA manufacturers to clean in the past. However, with the advent of no-clean solder pastes and fluxes and their forced continued Surface Insulation Resistance (SIR) improvement due to low standoff and bottom terminated components, have the enhanced properties of these modern formulations mitigated the need to remove rosin-based no-clean flux residues for the sake of electrical reliability? This paper will attempt to address this question by assessing the electrical reliability of no-clean solder paste flux residues using J-STD-004B SIR as the test method. In this work, IPC B-24 SIR coupons prepared with three commercially available rosin-based no-clean SAC305 type 4 solder pastes, two pastes classified as ROL0 or halogen-free and one classified as ROL1 or halogen-containing, reflowed with profiles with three different peak temperatures ranging from very cool to typical, will be compared to the electrical performance of clean bare IPC B-24 SIR coupons that have been exposed to the same reflow profiles as well as without any heat exposure.

While the intent of this paper is to show that cleaning is not always necessary for the sake of electrical reliability, without any doubt, there remain many scenarios where cleaning for the sake of removing the flux residues is appropriate such as applications involving conformal coating, underfilling, and high-temperature exposure (above the melting temperature of rosin), to name a few.

Every year, billions and billions of products are made and sold across the world. Each of these products, regardless of volume, are made in facilities that follow certain steps to assemble, test, and ship to customers. The steps that are taken to fulfill demand are an extremely interesting and valuable source of information. When modeled, simulated and analyzed, these steps can offer phenomenal insight on the overall process. This practice in the industry is called Discrete Event Simulation. Discrete Event Simulation, (namely DES) is the process of modeling a real-world phenomenon or system of operation as a sequence of discrete events. Discrete events in this context are described as instances that occur in a particular point in time with no change to the phenomenon or system between each event. Discrete Event Simulation is different than Continuous Event Simulation where the system is continuously changing due to a response to certain mathematical formulas and will not be covered in this paper. This paper will provide an overview of discrete event simulation in general, explain the different types of model taxonomy used in academia and industry, as well as discuss the importance and value of using these tools and practices in electronics manufacturing operations. Lastly, this paper will discuss challenges in adoption as well as a call to action for Discrete Event Simulation software providers and an outlook on where the industry is going from the perspective of Flex. In the context of this paper, “electronics manufacturing operations” refers to the assembly (both automated and manual), test (both automated and manual) and the shipping (both automated and manual) of electronic products.

Use cases, solutions and standards for single device traceability in the supply chain to enable root case analysis, recall containment, device pairing, yield and reliability improvement and liability protection.

Machine Learning 

Edge Computing

Edge AI

Demonstrated using a Case Study on HiP (Head in Pillow) defect detection

New product introduction at an Original Equipment Manufacturer (OEM) typically includes reliability testing in the form of thermal cycling. Samplings from the engineering models of a new product line were consistently failing the optical testing following the reliability testing. Cross sectioning revealed stress fractures in the solder joints of the LGA ceramic image sensor component. As the image sensor dominates one side of the PCA, the root cause appeared to be Coefficient of Thermal Expansion (CTE) mismatch between the FR4 material of the PCA and the ceramic body of the image sensor. As this new product line was to be high volume, the goal was to avoid introducing an additional component under fill process step and resolve reliability issues through basic SMT assembly processes at the Contract Manufacturer (CM).

A joint OEM-CM Tiger Team explored the contributions of both the solder paste volume and the reflow temperature profile to the robustness of the LGA solder joints. The stencil design aspect included the shape of the aperture and the resulting volume of solder paste deposited. The solder paste volume affects the standoff of the component from the PCA. The sensor manufacturer datasheet for the oven reflow profile allowed a range of temperature values, the most significant being the temperature cool down slope. The cool down slope affects the granularity of the solder joint. The CM’s team performed a DOE maximizing and minimizing both the solder paste volume and the temperature profile cool down slope combinations.

The DOE results trended towards higher paste volume and steeper temperature cool down slope. The risk of solder bridging using the higher paste volume was minimal, but the steeper temperature cool down slope produced unacceptable process voids. Therefore, the choice for optimal SMT process condition was a combination of high solder volume and lower temperature cool down slope. Passing results for optical testing post reliability testing, followed by cross section, validated this optimization. Introduction Reliability testing performed as part of new product introduction included thermal cycling to simulate long-term reliability of the soldering. For this product, the temperature range was -40°C to 85°C, with a cycle consisting of 15 minutes at low temperature, 5°C/minute rise for 25 minutes, 15 minutes at high temperature, 5°C/minute fall for 25 minutes, and repeated for 300 cycles. This testing simulates reliability for 8.6 years based on IPC-SM-785 and IEC 60068-2-14. The product was not powered during the thermal cycling. Following the reliability test, the product’s image sensor underwent optical testing. A significant number of the test samples failed.

In automotive applications, electronic products are subject to several loads, among which thermomechanical loads are particularly affecting the product reliability. Temperature cycling tests on free PCB aim to reproduce the thermal mismatch load at solder joint level, based on coefficients of thermal expansion but does not take into account the real mechanical load applied in the product. The latter, influenced by design elements like housing or screws, has to be determined separately for each product. The new proposed approach enables electronic component design for reliability by developing an experimental and simulation test method combining products relevant thermal mismatch and mechanical loads. For this, PCBs undergo an experimental bending test under temperature cycling. For each tested component and each mechanical load level, a lifetime loss-factor is determined. The influence of component positioning on PCB, i.e. orientation is also considered. Experimental bending test results are then combined with detailed simulation models for complex components, i.e. BGA, to establish Wöhler-like curves and lifetime models. The transfer of those generated models into relevant electronic products enables reliability prediction i.e. layout design. Moreover, bending test combined to temperature cycling allows the visualization of potential failure mode changes at high bending levels (i.e. IMC cracks). This is an advantage versus free PCB test to avoid field and test failures on product level by early detection of bending sensitive components. At long-term, this new method aims to reduce the experimental costs by using the generated lifetime models for further reliability predictions.

This paper presents assembly challenges and reliability evaluation by thermal cycling for a 2.5D [aka, System in Package (SiP)]in a fine pitch ball grid array (FPBGA). More importantly, it presents the effect of underfilling of the top CSPs assembled on to interposer on the overall SiP reliability behavior.  A large number of variables were considered in the design of experiment including evaluation of bare FPBGA without parts on interposer, FPBGA balls either with SAC305 or SnPb solders, FPBGA fully/partially populated with CSPs and flip chip (FC) die on FPBGA interposers, and CSPs with and without underfills on the SiP interposer. 
Assembly of mixed SiP packages becomes a challenging task and required to be characterized by X-ray for solder-joint quality and by Shadow Moiré analysis for warpage characterization. Acceptable assemblies with and without underfilling CSPs on interposers were then subjected to thermal cycling between–40C and 125C for reliability evaluation and failure-mechanisms assessment. Details of design, characterization by X-ray and Moiré,  as well as reliability behavior of the SiP FPBGA due to thermal cycling exposures are presented. Failure analysis results also presented covering evaluation by optical, scanning electron microscopy (SEM), X-sectioning, and dye-and-pry evaluation. The Weibull plots of cycles to failures for SiP FPBGA with SAC305 and SnPb balls and CSP assemblies with and without underfills were presented. Finally, generic discussions were presented on the positive and negative effects of underfills at assembly level and specific reasons for early failures of SiP FPBGAs with CSPs assembled on to interposer with underfill.

KEY WORDS: SiP, system in package, 2.5D, Ball grid array, fine pitch BGA, FPBGA, solder joint reliability, underfill, thermal cycle, thermal shock cycle, Moiré, dye-and-pry

Polymer Thick Film(PTF)-based printed electronics (aka Printed Electronics) has improved in durability over the last few decades and is now a proven alternative to copper circuitry. This paper discusses the use of jet-dispensed Surface Mount Technology(SMT)adhesives for increased durability, lower component cost, and new form factor printed electronics. Jet-dispensing enables higher assembly speeds, accurate placement of multiple adhesives, smaller surface mount device (SMD) and Z-axis registration tolerance.