A novel epoxy SAC solder paste TIM system has been developedwith the use of non-volatile epoxy flux. Cu filler was added to the solder paste, with Cu volume % of metal ranged from 17 to 60 volume % of metal. Formation of semi-continuous high melting Cu chain network was achieved, with the use of CuSn IMC bridges between Cu particles. This chain network, at sufficient concentration, serves as skeleton and maintains the shape of the sandwiched solder paste layer, thus prevented further spread out and outgassing upon subsequent SMT reflow process, and also allowed formation of TIM joint even in the absence of solderable metallization on flip chip and packaging housing. Presence of significant amount of ductile solder within TIM joint promises high resistance against brittle cracking under stress. The Cu content could be further optimized between 17 and 33 volume % of metal to avoid flux bleeding and maintain good epoxy adhesion between TIM phase and parts. The 20C thermal conductivity achieved was 6.1 W/mK andcould be up to about 13 W/mK with further epoxy flux optimization.

Industry 4.0, autonomous vehicles and 5G connectivity are driving a new Internet of Things (IoT) revolution. Assembly materials like thermal interface materials (TIMs) need to be selected keeping in mind both performance as well as economics viability. With higher volumes of various device designs, automated manufacturing and adaptable materials are also critical factors is the price-performance equation. Uniquely, liquid dispensed thermal interface materials (TIMs) are an optimal approach to address this convergence of high performance and cost-competitive manufacturing. Adaptable attributes – such as curable or non-reactive – make liquid TIM materials well-suited for a variety of applications. This paper presents the basic science behind liquid TIMs identifies key TIM characteristics needed to design and manufacture reliably and efficiently, and illustrates the relationship between material properties, performance and manufacturing compatibility. Fundamental differences between solid, pad-like materials and unfilled liquids will be highlighted.

Most dispensable thermosetting products are supplied as blends of monomers or pre-polymers. Curing involves a complicated chemical “dance” with a precise sequence of polymerization of one or more segments (such as “hard” and “soft” blocks) and the creation of chemical links between the segments (crosslinking or vulcanizing). The dance choreography is typically accompanied by a rising exotherm that accelerates each chemical reaction at different rates – and those rates differ below or above the steadily rising glass transition (Tg) temperature of the solidifying mixture. The entire cure dances to the tempo of the mixture’s temperature, impacted both by external heating and any cure exotherm. If the tempo is too fast or too slow the result can be an awkward performance, with the end-product having properties out of the intended specification.

Silicones dance to a different tune, as they are generally supplied already fully polymerized with a -120oC Tg and no appreciable exotherm. Properties are shown that demonstrate remarkable consistency once the siloxane degree of polymerization reaches even 50-100 Si-O units. Silicones therefore have less complicated chemistry of curing since many of their fundamental properties are already set as supplied, and therefore there are far less things that can go wrong. Addition cure silicones are shown to be cured over a very wide range of temperatures with minimal impact on properties and general time-temperature transformation (TTT) curve is presented. 

Curing is complicated chemistry – well, for most products anyway. Many thermosetting liquid materials such as epoxies and urethanes are supplied as quite complicated formulations of reactants that must be brought together in just the right combination to achieve the desired final cured properties. Furthermore, the proper cure schedule of time and temperature must be followed in rather strict accordance with the supplier’s instructions or quite divergent final properties may result. The rather narrow cure temperature processing windows that must be followed arise from the complicated mix of chemical reactions that must occur in just the right ways to achieve the hoped-for results. And for materials that strongly exotherm, even the quantity of material being cured must be factored in as it can significantly impact the temperature in the later stages of the material cure.

Light-curable materials can provide significant benefits over conventional technologies, including very fast tack free curing, lower operating costs driven by lower labor needs, space savings, lower energy demand, and higher throughput. Encapsulants are often required to protect PCB components against moisture, chemicals, and rapid and extreme temperature changes while providing mechanical support and electrical insulation. We have developed a light and moisture dual curable 100% solids encapsulant that exhibits an excellent balance of properties. While the key advantage to light-curable encapsulant is the ability to use a non-solvated “green” (100% solids) material, secondary moisture curing allows curing of the material in shadow areas–areas not available to UV light.  And, the secondary moisture curing material can be shipped and stored at ambient conditions, does not requiring cold shipping/storage. We will discuss the performance of this material against other light-curable materials as well as other types of encapsulants in reliability tests such as heat and humidity resistance (85 oC / 85 % RH), thermal shock resistance (-55oC to +125oC) and corrosion resistance against salt spray and chemicals.

Large data transmission continues to increase at the rate of 20% worldwide annually due to live video streaming, cloud storage, PDA usage, IOT, and other technologies. Electronic devices are getting smaller yet required to accommodate higher speeds and good signal integrity.  With 5G technology on the horizon there is heightened concern for signal loss affecting product performance. It is more important than ever to analyze loss factor at the earliest design stage. This analysis is done for the PCB materials by manufacturing electrical test coupons prior to building the PCB and evaluating the electrical performance. These coupons are designed and built with (TEG, test element group) structures which are ideal for measuring transmission loss. However, often these test PCBs use different lots of raw laminate materials which yield different results. Why? This study examines possible factors for these inconsistencies such as etched signal trace shape, surface treatment, and grain size.

Keywords: high frequency, strip line, transmission loss, surface treatment, copper foil, grain size, skin effect.

Chip components are important elements in electronic production since surface mount technology was introduced. Over the years, package size has constantly decreased. The small resistors and capacitors are still required, even if chip designs and integration rates for integrated circuits are improving almost constantly as well. 0201 packages are state-ofthe-art in electronic production and smaller versions enter the market rapidly. While production systems like screen printers and pick-and-place machines can handle the small chips perfectly, touch up and repair processes become more challenging and many questions arise. What are the obstacles in the rework of 0201 and 01005 components? Which strategies and equipment lead to successful repair of these extremely small and sensitive devices?

Industry demand for high-speed server product performance such as PCI express requires higher pin counts in order to support memory channels which in turn is driving pitch reduction in the printed circuit board(PCB).To provide better signal integrity for high-speed signals, ultra-low loss (ULL) PCB materials may need to be used, and back drilling is recommended to remove via stubs and minimize signal loss.  Back drilling is the process where by plated through holes(PTH)are drilled from the stub-side of the PCB with a larger drill diameter (i.e. back drill) to a specified depth in order to reduce the stub length. This improves signal integrity by minimizing interference or signal loss due to excess stub length. Current industry back drilling capabilities have supported greater than 1mm pitch with a minimum back drill-to-metal gap of greater than 0.15mm. For pitches < 1mm, the drill-to-metal gap will need to be reduced to less than 0.15 mm. In addition, primary drill(PD)diameters will need to scale down. These changes pose manufacturability challenges with primary drill registration and higher aspect ratios (i.e. PCB thickness/PD). Reduced spacing compounded with drill registration issues can result in exposed copper, slivers//clipped traces, and layer-to-layer misregistration. Industry PCB manufacturing capability and experience with these finer pitches is immature. Next-generation server platforms will push the limits of current PCB industry capabilities, creating a need to identify and provide solutions to enable future manufacturing technologies for server PCBs requiring < 1 mm (0.94 mm) pitch designs. This paper will assess PCB vendor drill registration capability and will also evaluate PCB reliability using electrochemical migration (i.e. conductive anodic filament or CAF) and via reliability (i.e. interconnect stress testing or IST) testing. PCB manufacturing capability will be characterized as a function of back drill-to-metal gap capability and provide potential solution paths to enable PCB suppliers to fabricate reliable 0.94 mm pitch server boards.

The move from Plated Through Vias (PTVs) to advanced HDI interconnects is challenging the electronics industry, not only due to the increased complexity of design and manufacturing, but even more due to the difficulties associated with screening and testing at every level: PWB, assembly, and system. Unlike PTVs there is no definitive cross-section quality criteria to tell good from bad, testing requires very specific conditions to detect fine separations caused by reflow, the high variation in failure response challenges typical sampling plans, and even known failures can be very difficult to locate electrically and/or in an x-section.

This paper uses examples from over 25 years of testing advanced interconnects including microvias to show not only how they fail but more importantly how a unique attribute of their failure curves can be used to advantage to assure reliable product in any operational environment. The importance of peak test temperature with sufficient dwell, continuous resistance monitoring, coupon design, coupon location, thermal profile, and choice of failure criteria is demonstrated. The Temperature Coefficient of Resistance (TCR) Measurement is explained as both a foundation for thermal cycling tests and an informative test in itself. IPC methods 2.6.26B, 2.6.27A, and 2.6.7.2 are compared, with recommendations to improve effectiveness. Finally, a simple approach to locate and x-section microvia failures every time is presented.