Welcome to IPC's collection of technical papers presented at conferences since 2002. You can search by author, title and keyword. You can also search for keywords and topics in the Tag field. Access to the papers is reserved for IPC members.

IPC 2610 - Documentation Package

Description With the advent of CAD and CAM tools,the need arose for a more complete method of data transfer. As layer count increased,the number of files increased. As trace size and spacing began to decrease,the Gerber file size increased. The need ... read more
Author(s)
Karen McConnell
Event
IPC Fall Meetings 2004

Design Technology,What Does the Roadmap Say?

Description X ... read more
Author(s)
Dieter
Event
IPC Fall Meetings 2004

Lead Free Process Transition Solder Paste Characteristic Assessment

Description The migration to Lead Free raw materials in the Electronics Industry will happen faster than the date proposed in the original draft of the legislation. A true Pb-free solution for product such as high end and volume server and desktop requires printed ... read more
Author(s)
Robert Farrell,Steve Beck,Richard Garnick,Paul,Wang,Ken Kochi
Event
IPC APEX EXPO 2004

Lead-Free Implementation: Drop-In Manufacturing

Description The Lead-free electronics manufacturing has become a reality. As of this writing,a few manufacturers have rightfully reported their total completion to Lead-free production across all facilities,and some have reached partial implementation. ... read more
Author(s)
Jennie S. Hwang,Kaihwa Chew,Vincent Kho
Event
IPC APEX EXPO 2004

Printed Circuit Board Reliability in High Temperature

Description This paper will demonstrate the effect high reflow temperatures in lead free processes will have on the reliability of printed circuit boards from a broad range of laminate materials for both traditional and lead-free processes. The focus will be on 24 ... read more
Author(s)
Arshad Khan,Rex Lam,Bruce Houghton
Event
IPC APEX EXPO 2004

New Developments in Polymer Thick Film Resistor Technology

Description Motorola has been using embedded polymer thick film resistors on immersion silver-plated copper terminations in products for four years,and in the past year other firms have begun using this technology in their products. It is available to any ... read more
Author(s)
Gregory Dunn,John Savic,Troy Bachman,Isao Morooka
Event
IPC APEX EXPO 2004

Decoupling with Anodized Ta

Description Novel configurations of decoupling capacitors were formed by anodizing Ta,resulting in Ta2O5 films 2000 Å thick and k = 23,giving about 110 nF/cm2. Since the dielectric is very thin,the parasitic inductance is almost unmeasurable,and is shown ... read more
Author(s)
L Schaper,R. Ulrich,D. Mannath,J. Morgan,K. Maner
Event
IPC APEX EXPO 2004

Performance of Polymeric Ultra-thin Substrates for Use as Embedded Capacitors: Comparison of Unfilled and Filled Systems with Ferroelectric Particles

Description We have previously published our work on developing thin substrates for use as embedded capacitor layers. Based on this work we have continued to characterize the performance and reliability of these materials. ... read more
Author(s)
John Andresakis,Takuya Yamamoto,Pranabes Pramanik,Nick Buinno
Event
IPC APEX EXPO 2004

“Built-In-Trace” Resistors

Description The newly developed Ohmega-Ply “Resistor-Built-in-Trace” technology uses low-ohmic resistive materials for embedded resistors congruent to the circuitry in a multilayer PCB or HDI substrate. High frequencies and miniaturization has created ... read more
Author(s)
Daniel Brandler
Event
IPC APEX EXPO 2004

Embedded Passives in High Layer Count High Reliability Printed Wiring Boards

Description This paper will discuss the use of thin film buried resistors and thin core plane pairs in high layer count high reliability printed wiring boards used in single and double sided surface mount assemblies. Very high thermal stress durability is ... read more
Author(s)
Michael G. Luke,Jeffrey C. Seekatz
Event
IPC APEX EXPO 2004

Design Considerations for Thin-Film Embedded Resistor and Capacitor Technologies

Description Embedded passives technologies can provide benefits of size,performance,cost,and reliability to high density,highspeed designs. A number of embedded passive technology solutions are available to the designer. Based on our ... read more
Author(s)
Percy Chinoy,Marc Langlois,Raj Hariharan,Mike Nelson,Anthony Cox,Tony Ridler
Event
IPC APEX EXPO 2004

Designing Embedded Resistors and Capacitors

Description Embedded passives,i.e.,resistors and capacitors built right into the printed circuit board substrate,is a rapidly emerging and pivotal technology for the PCB industry preceded only by the plated thru hole in the 50s and microvias in the 80s. ... read more
Author(s)
Richard Snogren
Event
IPC APEX EXPO 2004

Reliability of High Density,High Layer Count,Multilayer Backplanes

Description This paper discusses the work and testing performed to obtain extreme high reliability performance from high layer count, large panel format multilayer printed wiring boards that are used for backplanes in surface mount technology applications. ... read more
Author(s)
Jeffrey C. Seekatz,Michael G. Luke
Event
IPC APEX EXPO 2004

Via in Pad Study Evaluating the Impact on Circuit Design,Board Layout,Manufacturing,Emissions Compliance and Product Reliability

Description Driving factors for the use of via in pad technology include the growing trend towards more dense and complex printed circuit board designs as well as the need to minimize parasitic capacitance and inductance on high speed digital circuits. ... read more
Author(s)
Bruce Hughes,Dana Bell,Holly Mote,Trevor Bowers,David Nelson,Andy Gantt,Chuck Peltier
Event
IPC APEX EXPO 2004

Drawing Note Generator

Description This paper will describe the method used to automate drawing note creation at Lockheed Martin. It will discuss the reasons for the automation and some of the decisions that needed to be made before automation could take place. This paper will ... read more
Author(s)
Karen McConnell,Harry Finocchiaro,Scott Park
Event
IPC APEX EXPO 2004

NEMI Cost Analysis: Optical Versus Copper Backplanes

Description The outlook for optical PCBs is unclear for mainly three reasons: 1) today's limits for copper boards can be stretched with design and manufacturing improvements,2) the market demand for next generation,higher bandwidth telecom systems (in ... read more
Author(s)
David Godlewski,Nancy Chiarotto,Adam T. Singer,Kurt Wachler,Kurt Wachler,Harry Lucas,Gary Hoeppel,Dave Haas,David L. Wolf,John T. Fisher
Event
IPC APEX EXPO 2004

Creating a New Optoelectronics Standard: Specifications for Process Carriers Used to Handle Optical Fibers in Manufacturing

Description The lack of consistency and compatibility in process carrier designs was cited as an early barrier to automation in the nascent fiber-optics industry. Under the auspices of the National Electronics Manufacturing Initiative (NEMI),a working ... read more
Author(s)
Randy Heyler
Event
IPC APEX EXPO 2004

Is That Splice Really Good Enough? Improving Fiber Optic Splice Loss Measurement

Description Results from a National Electronics Manufacturing Initiative (NEMI) project,formed to improve aspects of fiber optic fusion splicing,are reported. The focus of this paper is ultra low loss splicing for telecommunications product assembly,with ... read more
Author(s)
J. Meitzler,L.Wesson,P. Arrowsmith,R. Suurmann,M. Rodriguez,D. Gignac,S. Pradhan,J. Garren,J. Johnson,T. Watanabe,E. Mies
Event
IPC APEX EXPO 2004

Non-Telecom Optoelectronics

Description When we think of optoelectronics in the USA,we automatically think of telecom applications. These fueled huge growth at the turn of the millennium,and even after the bubble burst in 2001-2,telecom represented a significant business and the ... read more
Author(s)
Alan Rae
Event
IPC APEX EXPO 2004

Mechanical Bending Technique for Determining CSP Design and Assembly Weaknesses

Description A cyclic board-bending technique has been developed to ensure a reproducible multiaxial stress state at the Chip Size Package (CSP) solder fillet. Mechanically stressing the package serves as a valuable tool to quickly determine ... read more
Author(s)
Mark R. Larsen,Ian R. Harvey,David Turner,Brent Porter,Jim Ortowski
Event
IPC APEX EXPO 2004

Reliability Assessment of CSP Underfill Methods

Description The miniaturization trend in electronics has proliferated the use of Chip Scale Packages (CSPs) in electronics assembly. CSPs used in portable devices are subjected to harsh mechanical and thermal conditions and underfill provides a dramatic ... read more
Author(s)
Mandar Painaik,Senthil Kanagavel,Daryl L. Santos
Event
IPC APEX EXPO 2004

Lead Free Assembly of Chip Scale Packages

Description Chip scale packages (CSPs) are widely used in portable electronic products where there is also a growing trend to lead free assembly. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, ... read more
Author(s)
Yueli Liu,Guoyun Tian,Shyam Gale,R. Wayne Johnson,Pradeep Lall,Larry Crane
Event
IPC APEX EXPO 2004

Are Lead-free Assemblies Especially Endangered by Climatic Safety?

Description The ever-increasing use of high frequency in high density interconnect (HDI) assemblies,combined with the worldwide move toward lead-free manufacturing,has initiated a closer scrutiny towards effective flux removal processes. Since ... read more
Author(s)
Andreas Muehlbauer,Helmut Schweigart,Umut Tosun,Stefan Strixner
Event
IPC APEX EXPO 2004

Lead-Free Soldering: DOE Study to Understand its Affect on Electronic Assembly Defluxing

Description Lead-free alloys under consideration have physical properties,which may directly impact industry standard electronic assembly cleaning processes. The purpose of this study is to evaluate how the use of nitrogen versus non-nitrogen reflow atmospheres affect the ... read more
Author(s)
Mike Bixenman,Dirk Ellis,Steve Owens
Event
IPC APEX EXPO 2004

Lead Free and Other Process Effects on Conductive Anodic Filamentation Resistance of Glass Reinforced Epoxy Laminates

Description Conductive Anodic Filamentation is a subsurface failure mode for woven glass reinforced laminates (FR4) materials,where a copper salt filament allows bridging between via walls or other copper conductors. In this study FR4 laminates,in the form of ... read more
Author(s)
Alan Brewin,Ling Zou
Event
IPC APEX EXPO 2004

Characterization of PCB Plated-Thru-Hole Reliability using Statistical Analysis

Description Various test methods are used to characterize the PCB plated-thru-hole reliability. One such method is the Interconnect Stress Test (IST). The results from this test are often used to qualify PCB materials and/or fabricators. This paper will discuss how ... read more
Author(s)
Mark J. Tardibuono
Event
IPC APEX EXPO 2004

Solder Joint Reliability Qualification of Various Component Mounting Modification Configurations Using Thermal Cycle Testing

Description The selection and use of solder joint modification configurations for printed wiring assemblies has traditionally been a design specific activity. The implementation and use of a standardized set of solder joint modification configurations on an industrywide ... read more
Author(s)
David Hillman,Jennet Kramerand,Bryan James
Event
IPC APEX EXPO 2004

Finite Element Analysis of Flip Chip Ball Grid Array Packages for BGA Life Prediction: 2D,3D or Axisymmetric?

Description A variety of mechanical and thermal stress related problems related to Flip Chip Ball Grid Array Packages (FCBGAs) are often solved by the Finite Element Method. Often,the question for the stress analyst is how to simplify the problem at hand ... read more
Author(s)
Virendra Jadhav,Sanjeev Sathe,
Event
IPC APEX EXPO 2004

Development of Epoxy Mold Compound for Lead Free Soldering of Fine Pitch and Stacked Die BGA Packages

Description A new,green epoxy mold compound has been developed to encapsulate fine pitch PBGA and 3D-stacked die CSP packages. When evaluated on these packages,the compound provided very good wire sweep performance. It also has the ability for ... read more
Author(s)
Chinnu Brahatheeswaran
Event
IPC APEX EXPO 2004

Design and Development of a High Performance Wirebond BGA Package

Description As the need for higher performance,higher I/O count packaging solutions at lower costs continues to grow,opportunities exist to support these applications with higher performance wire bonded packages,as an alternative to some of the more expensive FlipChip solutions. ... read more
Author(s)
Clifford R Fishley,Abi Awujoola,Len Mora,Alex Lacap
Event
IPC APEX EXPO 2004

Lead Free Conversion Analysis for Multiple PWB/Component Materials and Finishes using Quality and Reliability Testing

Description The world-wide movement to phase out lead from electronic products presents many challenges for companies throughout the electronics supply chain. The University of Massachusetts Lowell has brought together nine Massachusetts firms to ... read more
Author(s)
Sammy Shina,Liz Harriman,Todd MacFadden,Donald Abbott,Richard Anderson,Helena Pasquito,Marie Kistler,David Pinsky,Mark Quealy,Karen Walters,Richard McCann,Al Grusby
Event
IPC APEX EXPO 2004

Development of Assembly and Rework Processes for Large and Complex PCBs Using Lead-Free Solder

Description The continued functional densification and integration in networking products is driving the need to study large form factor printed circuit boards that use high I/O packages (either ceramics column grid arrays,CCGA,or plastic ball grid array, ... read more
Author(s)
David A. Geiger,Jin Yu,Dongkai Shangguan
Event
IPC APEX EXPO 2004

Assembly,Rework and Reliability of Lead-free FCBGA Soldered Component

Description Movements to lead-free assembly are being influenced by legislative and market requirements. Specifically Europe has passed legislation requiring the removal of lead from electronics assembly by 2006. Also,the perceived marketing advantage ... read more
Author(s)
Sam Yoon,Roy Wu,Jasbir Bath,Chris Chou,Samson Lam
Event
IPC APEX EXPO 2004

Effect of Lead-Free Alloys on Voiding at Microvia

Description For SnAgCu solders,the voiding rate at microvia was studied with the use of simulated microvia,and was the lowest with 95.5Sn3.8Ag0.7Cu and 95.5Sn3.5Ag1Cu. The voiding rate increased with decreasing Ag content from 3.5Ag,mainly due to ... read more
Author(s)
Arnab Dasgupta,Benlih Huang,Ning-Cheng Lee
Event
IPC APEX EXPO 2004

Lead-Free and Mixed Assembly Solder Joint Reliability Trends

Description This paper presents a quantitative analysis of solder joint reliability data for lead-free Sn-Ag-Cu (SAC) and mixed assembly (SnPb + SAC) circuit boards based on an extensive,but non-exhaustive,collection of thermal cycling test results. The ... read more
Author(s)
Jean-Paul Clech
Event
IPC APEX EXPO 2004

A Reliability Comparison of Different Lead-Free Alloys and Surface Finishes in SMT Assembly

Description As we inch towards the somewhat shifting deadlines towards lead (Pb) restriction in Japan and Europe,there is an increase seen in the amount of studies performed for electronics assemblies soldered with Pb-free alloys. This paper presents results of ... read more
Author(s)
Jignesh Rathod,Daryl Santos,Prashant Chouta,Joe Belmonte,Alan Rae
Event
IPC APEX EXPO 2004

Reliability Testing and Failure Analysis of Lead-Free Solder Joints under Thermo-Mechanical Stress

Description The commercial use of lead-free solder has been making significant gains worldwide in recent years. To identify the effects of thermo-mechanical stress on Sn-Ag-Cu and Sn-Zn-Bi solder with different lead finishes (Sn-10Pb,Ni/Pd/Au plating),we ... read more
Author(s)
Hirokazu Tanaka,Yuuichi Aoki,Makoto Kitagawa,Yoshiki Saito
Event
IPC APEX EXPO 2004

Effect of Transient Thermal Profiles in Wave Soldering Processes on Connector Performance

Description Developing lead free connector products involves at least two distinct steps: removing the lead from the product and ensuring the product has sufficient thermal stability. Lead is most commonly found in terminal finishes and has been removed from ... read more
Author(s)
Alexandra L. M. Spitler,Robert D. Hilty
Event
IPC APEX EXPO 2004

Erosion of Copper and Stainless Steels by Lead-Free-Solders

Description An issue that has emerged from the increasing use by the electronics industry of lead-free solders in mass production wave soldering is the erosion of the copper of printed circuit board patterns and component terminations and the stainless steel of ... read more
Author(s)
Keith Sweatman,Shoichi Suenaga,Masaaki Yoshimura,Tetsuro Nishimura,Masahiko Ikeda
Event
IPC APEX EXPO 2004

Test and Inspection of Lead-Free Assemblies

Description Major industrial nations,around the world,are rapidly moving to eliminate lead from the electronic manufacturing processes. While some companies are taking advantage of the situation and are using “lead-free” as a major marketing initiative in the ... read more
Author(s)
Michael J Smith
Event
IPC APEX EXPO 2004

Tin Whisker Growth - Substrate Effect Understanding CTE Mismatch and IMC Formation

Description The hypothesis that the “whisker growth phenomenon” in electrodeposited tin is a re-crystallization process driven by stress has gained popularity among leading research institutes and industrial laboratories. However,there exist varying opinions as ... read more
Author(s)
Y. Zhang,C. Fan,C. Xu,O. Khaselev,J. A. Abys
Event
IPC APEX EXPO 2004

Conquer Tombstoning in Lead-Free Soldering

Description Tombstoning of SnAgCu is affected by the solder composition. At vapor phase soldering,both wetting force and wetting time at a temperature well above the melting point have no correlation with the tombstoning behavior. Since tombstoning is ... read more
Author(s)
Benlih Huang,Ning-Cheng Lee
Event
IPC APEX EXPO 2004

FPGA on Board

Description Whilst the number of new ASIC designs has decreased over the last couple of years,there has been a dramatic increase in the number of FPGA designs implemented. Not only have the number of designs increased rapidly,the complexity and also the ... read more
Author(s)
Rick Stroot
Event
IPC APEX EXPO 2004

Insertion Loss,Eye Pattern and Crosstalk Analysis of Mixed Dielectric Striplines (Simulation and Measurement)

Description As digital data rates reach 5Gb/s,10Gb/s and beyond,digital designers are finding it increasingly difficult to meet their design constraints using FR4. While there are a host of alternative materials available,cost constraints often prohibit the use ... read more
Author(s)
Noel Hudson,Tammy Yost,Gregg Wildes
Event
IPC APEX EXPO 2004

Signal Integrity Analysis Techniques used to Characterize PCB Substrates

Description The electrical properties of PCB substrates are one of the primary factors used in designing high-frequency printed circuit boards. The loss tangent is the electrical property used by material suppliers to characterize the signal integrity of the PCB ... read more
Author(s)
Sean S. Mirshafiei,Dan Enos
Event
IPC APEX EXPO 2004

Automatic Generation of RC Network Models for a BGA Package

Description The need for dynamic compact models for Integrated Circuits (ICs) is a well-recognized problem in electronics cooling simulations of electronic systems. Simplified thermal models have been reported in literature to simulate steady-state and ... read more
Author(s)
Manoj Nagulapally,Sam Z. Zhao
Event
IPC APEX EXPO 2004

Advanced Microvia Design

Description Microvias are the fastest growing new technology for printed circuits. Once you understand the basics,the advanced topics bring the real advantage to light. This talk will highlight the procedures and conditions that designers needs to consider ... read more
Author(s)
Happy Holden
Event
IPC APEX EXPO 2004

High Frequency Conductor Loss Impact of Oxide and Oxide Alternative Processes

Description In most of today's high speed digital interconnects,the signal loss associated with the printed circuit board (PCB) is the dominate factor. Material selection,trace geometry,and choice of copper foil all play a role in establishing the signal loss ... read more
Author(s)
Gary Brist,Don Cullen
Event
IPC APEX EXPO 2004

Peroxy-Sulfuric Oxide Replacements – A Pathway to Improved Technology for Fine Line Processes

Description Traditional reduced black oxide processes for inner layer bonding have been superseded by a newer generation of peroxidesulfuric texturing processes. These lower cost processes,based on an organically controlled microetch,have proven to be ... read more
Author(s)
Abayomi Owei,Hiep Nguyen,David Ormerod,Jeff Sargeant
Event
IPC APEX EXPO 2004

PTFE Wettability for Electroless Copper and Direct Metallization

Description PTFE material is very hydrophobic and among the most difficult to deposit electroless copper or direct metallization. These materials have very low friction,which makes a surface non-wettable. Plasma technology has the ability to create wettable ... read more
Author(s)
Lou Fierro
Event
IPC APEX EXPO 2004