Today’s SMT assemblies are being driven toward SMD’s with higher lead densities as well as smaller packages.
This places additional performance requirements on the printing process. The stencil printing process has a major
influence on SMT assembly yields. It is important to consider stencil design,aperture design,and stencil printing
performance when selecting a stencil. This paper will focus on stencil printing performance and,specifically,how to
choose the correct stencil to increase SMT assembly yields.
Stencil print performance is evaluated over a range of stencil technologies including: Electroform,Laser-cut,Lasercut
with Electropolish and Nickel plate,and Precision Chemically - milled stencils. A total of 23 different stencils
were evaluated in the study. These stencils are made using the exact same Gerber file. Stencil printer set-up,solder
paste,and solder volume measurement set-up is identical for the stencils. Print studies were performed in an
independent test laboratory. Solder volume is measured for 8 different device types,including the following: 0201,
uBGA 20 mil pitch,0402,CBGA 40 mil pitch,16,20,25 mil pitch QFP’s and uBGA 31mil pitch. Stencil print
performance will be evaluated by measuring solder paste volume,solder paste volume dispersion,misprints
(bridging or insufficients) and positional accuracy of the stencil apertures. Physical properties of each stencil such as
aperture size,aperture wall smoothness and aperture cross section are measured. This information will be used to
predict SMT assembly yields for the array device types listed above. The yield data is then used to predict rework
cost related to the different types of stencils included in the study. Paste relax and recovery tests using three solder
paste types and five stencil types is reported. In this test dwell time between prints is varied from 15 minutes to 90
minutes.

In the complex electronics industry,supply chain costs can have a major impact on a company’s profitability. Like
the industrial supply chain,where costs are estimated to account for as much as 8% of a company’s operating
income,the electronics supply chain has many points that can affect the bottom line.
Assembly manufacturers,suppliers and contract manufacturers can positively impact their bottom lines by
optimizing their supply chains. Opportunities are greatest when companies focus on the big picture and make
improvements that benefit the entire operation.
One example of a supply chain improvement that can pay big returns for electronics component assemblers is
something they might not have considered: a returnable packaging system.
Returnable packaging systems contribute much more than durable,ESD-protective containers for shipping
components. They deliver cost-savings and efficiency at multiple points on the supply chain. The improvements
can add up to much greater financial benefits than most companies realize,including:
• Cuts in the Cost of Goods Sold
• Limits on Selling,General and Administrative Expenses
• Reduced Capital Costs
This paper presents a new way of looking at returnable packaging: how it can optimize the supply chain,where it
improves the bottom line,and how companies can achieve maximum return on their investment.

Solder paste for use in wafer bumping applications is becoming an extremely viable technology. Yields from solder
paste printing applications are approaching that of typical bumping technologies. The lower cost associated with
printing technology is driving the flip chip industry to adopt this low-cost method of bumping. This investigation
examines the variables of wafer bumping using solder paste printing techniques. A multiple factor designed
experiment was used to optimize printing parameters for solder paste deposition. Factors examined included: types
of solder paste,powder distribution,stencil type,print speed,and print pressure. The responses measured included
the volume of solder paste deposited and variability of the solder paste depositions.

The relentless trend for smaller,lighter,cheaper consumer products continues to fuel the demand for new,smaller,
efficient electronic packages. In recent years wafer level packaging concepts have emerged,providing multiple
design wins in terms of form factor and production costs. Performing all processing at the wafer level prior to dicing
provides obvious cost advantages whilst the WLP footprint offers a 1:1 component to package ratio.
Solder bumping usually represents the final stage in the WLP assembly process prior to dicing. Standard solder
paste print and reflow techniques can be utilised but the resultant bumps invariably fall below specifications due to
process limitations. More commonly,dedicated equipment sets that place pre-formed solder spheres onto the wafer
are used.
This paper details work undertaken to combine the benefits of standard stencil printer technology with that of solid
solder sphere placement to enable the development of a low cost,flexible system for the bumping of wafer level
packages. In addition,an alternative print & reflow technique based on an extrusion concept was also investigated.
The two techniques are compared for the bumping of a 0.5 mm pitch WL-CSP product.
The work undertaken forms part of the European funded IST-2000-30006 "Blue Whale" programme which is
concerned with developing next generation wafer level packaging for handheld applications in a LAN environment.
Project partners include Philips CFT,Shellcase,Technical University of Berlin,Technical University of Delft and
DEK Printing Machines Ltd.

A technique that enhances the release of solder paste from stencils during the print process has been developed. The
technique is based on applying variable high frequency and low amplitude vibrations to the stencil during the
stencil/substrate separation sequence. The effects of the technique are demonstrated in the context of bumping
wafers. It is shown that the enhanced print technique produces wafers with fewer defects,greater bump heights and
better height uniformity than when conventional stencil printing is used without the enhancement technique.

Chip Scale Package (CSP) technology is growing at a rapid pace since its emergence in the electronics
manufacturing industry. As the solder joint size decreases,it has become apparent that underfill is necessary to meet
certain reliability standards with CSPs,specifically drop testing. The need to underfill the CSP package has exerted
the same drawbacks that are involved in flip chip assembly. No-flow underfills pose potential in this area as they can
be incorporated into the standard SMT process with no post reflow processing. Most new materials simultaneously
reflow and cure in the same reflow process used for standard SMT solder pastes. This work presents a reliability
study of several commercial no-flow underfills and compares these CSPs to CSPs assembled without underfill and
CSPs assembled with conventional fast-flow,snap-cure underfills. Samples were built using solder paste only,flux
only,combinations of conventional underfill and solder paste or flux,and no-flow underfills. The reliability tests
include liquid-to-liquid thermal shock (-40oC to 125oC) and board level drop tests (6-feet). Samples assembled with
underfilled were benchmarked against the samples that were not underfilled. The CSP test vehicles consisted of a
printed circuit board with 10 CSPs having 84 I/O and a 0.5-mm pitch. Through these tests,it has been determined
that no-flow underfills can pass over 1000 cycles in liquid-liquid thermal shock,the typical standard for
package/product qualification. Samples assembled with no-flow underfills also exhibited an increase in reliability
during drop testing as compared to non-underfilled samples. The reliability data shows that no-flow underfill
implementation on CSP increases reliability as compared to non-underfilled samples.

Underfill technology has been used to minimize the mismatch of the Coefficient of Thermal Expansion (CTE)
in flip chip technology. An extension of this application has been used to increase the mechanical strength of
Chip Scale Packages (CSPs).
This paper will discuss the impact of non-reworkable and reworkable underfill,and corner-bonding on the mechanical
strength of CSPs. Reliability tests performed include drop,shear,bending and thermal shock tests. The
goal is to understand the reliability and degree of protection each of these underfill material offers.

The trend in optical communications is toward all-optical Networks,which transmit,manage and route traffic over
extended distances in the optical domain,without the need for power-hungry and bandwidth-limiting electronic
switching equipment. The Design & Technology Center at Solectron in Bordeaux has reached a trade agreement
with a start-up company for the entire development of new optical switches. This start-up develops an original
switch technology which is based on the thermo-optic effect. The Design & Technology Center has taken up the
challenge for the entire packaging developments. These developments take into account the design and assembly of
the electronic cards,the mechanical housing,and the interconnection of the optical switch,consisting of a 5” inches
silicon wafer with a pigtailed optical fiber ribbon. All the engineering teams of the Design & Technology Center
have contributed to these developments. The purpose of this paper is to review the integration of a silicon wafer
inside a package using the wire bonding technique. In a first part,the packaging problematic is presented and more
specifically the packaging for optical devices. Then the baseline process is reviewed with emphasis on Flexible PCB
design & manufacturing,wire bonding and encapsulation processes.

The outgassing level of materials (such as adhesives,composites,plastics,etc.) that are used to assemble and
construct optoelectronic packages,sub-assemblies,and other electronic materials is becoming more of a necessary
design variable. The standard methodology to measure outgassing levels within electronics manufacturing utilizes
the NASA ASTM E-595 method,which generates only two numbers: total mass loss (TML) and collected volatile
condensable materials (CVCM). The downside to this methodology is that it cannot be modified to meet the realworld
operation conditions of the assembly nor can it tell you the identity of the outgassing compounds. Often,
being able to identify what is outgassing is much more important than the total volume of outgassing. This
presentation will present a description and various applications of the dynamic headspace (DHS) outgassing
analytical methodology that can study any material,in any construction,at any temperature,at sub-nanogram levels,
with complete compound quantitation and identification. The analytical system consists of an outgassing manifold
followed by gas chromatography with mass spectral detection. This technique is based upon testing required by all
Tier I and Tier II OEM suppliers within the hard disk drive industry.

Electronic devices become more and more smaller. Electronic assemblies are sensitive against electrostatic discharge
just as much as its smallest and most sensitive element. So protection systems are necessary in all areas,where these
devices and assemblies are handled and used. Sometimes it seems to us,that steps are not any more necessary. But
the last time showed us,that every time new sources for electrostatic charge can be developed,which have not been
imagined until now. A person can be equipped ESD - required very good,but the whole environs of the proceeding
is a danger,which become bigger and bigger. Especially the activities,which are made automatically,cause big
damages at the devices and assemblies. In the first part necessary steps are described,which are needed to equip
persons and working places. The second part deals with machines and assemblies. Especially there the most
problems come out. In the last part an overview is given about the necessary test methods.