IPC High Reliability Forum

Designing electronic assemblies for high voltage (HV) applications (800-1200V) in electric vehicle (EV) units presents unique reliability challenges. Recalls by EV Original Equipment Manufacturers (OEMs) have often been linked to particle-induced electrical breakdowns and moisture ingress in OCB/DC/DC units, leading to contamination and increased failure risks. The absence of standards like IEC 60664, which covers electrochemical migration (ECM), further complicates the design landscape for engineers, making it difficult to ensure proper insulation in the HV range.

In addition to common failure mechanisms under humidity, such as ECM and creep corrosion, emerging issues like Anodic Migration Phenomenon (AMP) due to insulation material aging pose further challenges. These failures can manifest later, causing short circuits, while particles can lead to arc discharges and thermal incidents. Addressing these risks is crucial in design Failure Mode and Effects Analysis (FMEA).

A new analytical approach to isolation coordination addresses these challenges by considering the assembly's conductivity under environmental influences. This method allows for deriving limits for ionic, filmic, and particulate contamination, as well as the insulation materials to be used, based on HV reliability tests.

The presentation will cover the use of ion chromatography, CoRe-/iodine vapor tests, and fritt-voltage analysis, illustrating their application through examples. Implementing these analytical techniques in the electronic assembly process can lead to significant cost savings while meeting increased reliability requirements. This approach is essential for next-generation powertrain (PT) units to enhance the acceptance and safety of EVs.

Dr. Denis Barbini is an esteemed electronics manufacturing and assembly professional. Formerly the Associate Director of the A.R.E.A. Consortium, he led the identification of critical needs in emerging technologies and assembly processes. With extensive hands-on experience, Denis has provided invaluable guidance and solutions to companies worldwide. His expertise lies in implementing cost-effective, reliable, and robust processes for electronic devices. Recently, he transitioned to the role of ZESTRON's Technical Solutions Manager, leveraging his 25 years of experience to drive the development of critical projects and explore new industry sectors.

A certain level of voiding both in surface-mount as well as through-hole solder joints generally has no negative impact on assembly reliability under thermo-mechanical or mechanical loads. Yet, concerns that excessive voiding may affect assembly reliability exist among various stakeholders in the supply chain, from Tier2 to OEMs. This calls for: (i) Common requirements for voiding levels for different solder-joint geometries; (ii) Non-destructive methods for the quantitative assessment of voiding.

This works summarizes previous work on the impact of voiding on assembly reliability and explains how standards have been updated in the light of the existing data.

It also provides an assessment of the current opportunities and challenges in assessing voiding levels non-destructively by X-ray inspection: Typical X-ray inspection systems used nowadays do not generally satisfy common requirements on gauge repeatability and reproducibility (gauge R&R) when employed to assess voiding in solder joints. An outlook towards the use of artificial intelligence, which can provide an opportunity to overcome weaknesses of traditional image analyses approaches, will also be given.

Norbert Holle got his diploma in process technology at RWTH Aachen, Germany with diploma thesis at NTH Trondheim. In 2000 he received a PhD on “Investigations on the technical implementation of photobiological hydrogen production” at RWTH Aachen. In 1999 he started at Robert Bosch GmbH, Stuttgart as a research engineer with a focus on thermal high temperature processes for metals and ceramics. Since 2008 Norbert is working as a development engineer for assembly and interconnect technology. His main fields of experience are solder paste, SMT and reflow process topics, soldering defects (esp. voiding) and interactions of process - materials - PCB. 

Since the first via structures made with eyelets, the Electronics Industry has used microsections after thermal stress to evaluate quality after exposure to a simulated component attachment process.  As via structures have become increasingly complex and the component attachment processes more demanding, the thermal stress microsection has shown its inability to adequately meet the needs of the industry in determining via structure quality.  Over the last decade there has been a concerted effort to find a reasonable alternative the Thermal Stress microsection and to include a reliability aspect to the evaluation that is not as costly and time consuming as dual chamber thermal shock.  This presentation will touch on these efforts, test methods and set expectations for the latest methodologies that evaluate Solder Process Survivability, Reliability and Robustness of via structures.

Bob Neves is founder and Chairman/CTO of Microtek Laboratories & Reliability Assessment Solutions. He served as IPC Board Chair, and earned IPC Hall of Fame, IPC Presidents & Dieter Bergman IPC Fellow awards. He served as Chairman of IPC's TAEC, Rigid Board General Committee, HDI General Committee, Rigid Board Test Method Task Group, IEC TC91 Working Group 10 PCB Test Methods. He has participated on more than 50 IPC Technical Committees & has published dozens of articles and technical papers about Reliability, Testing, Test Methods & Failure Analysis & is the author of the PCB Acceptability section in Coombs “Printed Circuit Handbook” Sixth Edition.

A certain level of voiding both in surface-mount as well as through-hole solder joints generally has no negative impact on assembly reliability under thermo-mechanical or mechanical loads. Yet, concerns that excessive voiding may affect assembly reliability exist among various stakeholders in the supply chain, from Tier2 to OEMs. This calls for: (i) Common requirements for voiding levels for different solder-joint geometries; (ii) Non-destructive methods for the quantitative assessment of voiding.

This works summarizes previous work on the impact of voiding on assembly reliability and explains how standards have been updated in the light of the existing data.

It also provides an assessment of the current opportunities and challenges in assessing voiding levels non-destructively by X-ray inspection: Typical X-ray inspection systems used nowadays do not generally satisfy common requirements on gauge repeatability and reproducibility (gauge R&R) when employed to assess voiding in solder joints. An outlook towards the use of artificial intelligence, which can provide an opportunity to overcome weaknesses of traditional image analyses approaches, will also be given.

With a Diploma in Physics (University of Bayreuth, Germany) and a Doctoral degree in Chemistry (University of Stuttgart, Germany, 2002), Udo has profound knowledge in materials science and technology. He joined the Mobility Electronics Division of the Robert Bosch GmbH in 2012, where he now is responsible for Printed Circuit Board Technology Development. He is co-author of more than 90 scientific and technical papers and has given various invited lectures during scientific and technical conferences.

More information coming soon!

Steven Dirkes, a Quality Assurance Specialist, plays a crucial role in assessing and evaluating service quality and also implements initiatives to enhance service delivery, contributing to better health outcomes and safer communities. 

Printed circuit boards (PCBs) for automotive ECUs and communication modules are becoming smaller, higher density components, and embedded component technology is progressing. Components mounted on these PCBs generate heat, mostly transferred from the components to the PCBs. Therefore, it is necessary that not only the heat on the component surfaces be dissipated into the atmosphere or into the heat sink, but also the heat within the PCB, and the thermal design of mounted PCB has become more significant in recent years. In addition, to ensure high reliability and safety of PCBs, insulation materials for PCBs that can handle high voltages of 1,000 Volt or more are required.

Conventional heat-dissipating materials include TIM sheets and heat-dissipating grease, which are relay materials used to dissipate heat from the component surface to the heat sink, not the PCB, and have thermal conductivity but no insulation properties for consideration.

Based on our intensive study, we have developed a new material that has excellent thermal conductivity to dissipate heat from PCBs and high insulation properties, and can be easily printed on PCBs. This material is a uniformly dispersed ink consisting mainly of thermal curable resin and thermally conductive filler. It can be applied by general silk screen printing (like legend ink) as listed in the IPC standard, and is a permanent, fully cured coating (Tg:190℃), which is different from TIM sheets and grease that contain volatile components and change state. The cured film has a thermal conductivity of 3.3 W/mK and a dielectric breakdown voltage of 6,600 Volt per 100 μm film thickness. The appearance of the coating film is glossy, with a surface roughness (Ra) of less than 1.0 μm. The test using the coating film and an LED-mounted PCB has demonstrated that it effectively dissipates the heat from the PCB.

Takenori Kakutani is Business Development Leader of Taiyo Ink Mfg. Japan. Since 2005, he joined the Taiyo Ink, where he has been engaged in the R&D and the application of solder resist and various insulating materials for PCBs. He worked as a visiting engineer at the 3-D Packaging Research Center, Georgia Tech, Atlanta, US, from 2019 to 2021. He is currently involved in research marketing and product proposals of PCBs and IC packaging for automotive applications. He is a member of the Japan Institute of Electronics Packaging (JIEP) and the IPC standards.

X-ray inspection has become an increasingly common process control methodology in the past decade of electronics manufacturing. This has led to questions of how solder joint voiding impacts solder joint reliability. A significant amount of investigative work has been done to add to the industry knowledge, but there is still work to be done. This paper will review the IPC-J-STD-001 requirements concerning X-ray methodologies, the X-ray recommendations in Appendix C, the reliability papers for surface mount joints, and the practical application of X-ray inspection in a typical factory environment. This paper explains the intent of the J-STD-001 teams’ inclusion of their X-ray applications, the history of why there are voiding requirements for BGAs and BTCs, and the future of other voiding requirements that need to be addressed.

Tim Pearson is a Materials and Process Engineer in the Advanced Operations Engineering department of Collins Aerospace in Cedar Rapids, Iowa. Mr. Pearson graduated from Iowa State University with a BS in Materials Science and Engineering. Tim began his career as a Thin Films Engineer at Texas Instruments in a 300mm wafer fab. Tim has been working for Collins Aerospace (formerly Rockwell Collins) since 2015. In his current role, he helps develop new manufacturing processes, troubleshoots production issues, and does root cause analysis of failures related to soldering. He is a member of SMTA and IPC.

Electronics component packages have changed dramatically over the last 20 years in the drive for smaller, more capable electronics products. While much of that development was evolutionary, with similar packages offered in smaller formats, manufacturers have more recently created a multitude of unique package styles, particularly in the group of Bottom Termination Components. Industry documentation has struggled to keep up with the development of the component manufacturers, so it is often left to the assembler to decide how best to install these package styles. Changes to solder alloys and component finishes have increased voiding in general, and these new packages present challenges to the electronics assembler to ensure low voiding and robust solder connections that also provide an adequate thermal path. This presentation will discuss the challenges of assembly and solder joint evaluation and will present potential options for assembly improvement.

Ben has worked in the electronics industry for 23 years and is currently a Fellow at Lockheed Martin. He has experience in a variety of manufacturing assembly processes, with a prime focus on circuit card assembly. He has led numerous internal research projects related to soldering and solder joint reliability, as well as participating in several industry round robin studies. Ben is an active participant on several industry standard committees and is currently the Chair of IPC's Pb-free Electronics Risk Management (PERM) council.

What is electronic reliability, and how is it measured?  How do solder alloys and fluxes affect reliability?  This presentation addresses these questions from a solder and flux perspective.  High reliability alloys are used to improve the lifespan of electronics in “harsh environments.”  Low temperature alloys (peak reflow < 200 °C) are used to reduce heat related defects during manufacturing.  No clean solder pastes and fluxes are formulated to optimize soldering performance and leave residues that are “high reliability.” 

High reliability and low temperature solder alloys include elements to increase strength, improve compliance, and control melting point.  No clean solder pastes and fluxes are formulated to enhance solder joint creation and to be “safe” to leave on the printed circuit board assembly (PCBA).   These materials will be discussed, and reliability data presented.  The goal is to give an overview of solder alloy and flux contribution to reliability of electronics. 

Tony Lentz began his career in the electronics industry in 1994 as an engineer at a PCB manufacturer for 5 years. From 1999 to 2012, he worked for FCT Companies as a laboratory manager and facility manager. Since 2013, Tony has focused on field application and R&D for FCT Assembly solder and stencil products. He has written and presented many papers at industry events. Tony is the chair of the IPC J-STD-004 task group and vice-chair of the IPC J-STD-005 task group. He is a speaker of distinction with SMTA and holds B.S. and M.B.S. degrees in Chemistry.

Standard test methods provide product developers with information regarding materials' suitability for different purposes. Typically, current standards are suitable for determining the mechanical properties of new materials. However, in the case of electronic textiles (E-Textiles) and wearable technology (wearables), adding conductive components with added functionality makes utilizing textile standards difficult, and these standards will not provide information on mechanical and electrical properties of conductive elements. New standards for E-Textile and wearables testing are needed to ensure product developers can obtain the information necessary to make informed decisions about new products. Standards organizations such as the American Society for Testing and Materials (ASTM) and the Institute for Printed Circuits (IPC) are working on new methods for testing E-Textiles and wearables but must ensure the tests are rugged before publication and industry adoption. This study focuses on performing a ruggedness test for a new IPC test method for abrasion resistance of E-Textiles.

Erin Tillery is a graduate student at the NC State University Wilson College of Textiles working towards a Ph.D. in Textile Technology Management. Her research is focused on technology transfer in the textile industry, and she is currently working on projects related to E-Textiles and wearable technology. Her former work at Mississippi State University during her undergraduate and master's degrees includes work with new test methods for E-Textiles, creation of new wearable technology products, and wearables for human performance monitoring.

Check-in & Networking Breakfast

The Old and The New Come Together (Voiding and Other Challenges)

Speakers: 

• Tony Lentz, FCT Solder: Reliability of Electronics from a Solder and Flux Perspective
• Udo Welzel, Robert Bosch: Voids in Solder Joints: The Past, the Present and the Future
• Ben Gumpert, Lockheed Martin: BTC Assembly and X-Ray Challenges
• Tim Pearson, Collins Aerospace: Overview of using X-ray Inspection in Assessing Solder Joint Quality
• Panel Discussion: What Math is Required to Assess 75% Hole Fill?

Networking Break with Exhibitors

THE KEYNOTE and MORE

More information coming soon!

Is it High Voltage?

Speakers:

• Denis Barbini, Zestron USA
• Steven Dirkes, United States Department of the Army
• Takenori “Kenny” Kakutani, Taiyo Ink

Networking Lunch

Networking Break with Exhibitors

What’s New Now?  - E-Textiles/Advanced Technology/Design 

Speaker:

• Erin Parker Tillery, Ph.D. Student, Textile Technology Management

Reception

Check-In & Networking Breakfast

Here Comes the Testing and Related Challenges

• Panel Discussion: ROSE Testing
• Discussion: EE and an Industry Expert discussion on 80 year old test methods and 40 year old data - How do they play in todays industry?

Networking Break with Exhibitors

What Now? The Future is Calling

• Wrap Up Panel: What action do we take to preserve the industry?

Networking Lunch Buffet

Thank you for participating in the event!