Aerospace Defense High Performance (ADHP) electronics products primarily use tin-lead solders,but electrical and electronic component finishes (i.e.,platings) increasingly are designed for lead-free solders. The knowledge-gap on tin-lead integrity with new component finishes is growing over time. Also,the reworking of components to make them tin-lead compatible presents a component reliability risk. Therefore,it is important to understand and overcome the interfacial reliability risk for every combination of solder alloy and component finish used in ADHP products. The intermetallic compounds,which nucleate and grow during the soldering and use environments of electronics hardware,are of two general types. These are,1) Precipitation Compounds and 2) Diffusion Compounds. The precipitation compounds occur during the soldering process. The diffusion compounds can begin during the soldering process,and can grow during the environmental exposure of the solder connection to the product application (time at temperature,temperature cycling). We report numerous material combinations of soldering alloys and plating metals,where a common finding is that the growth of the diffusion compounds,at the solder-to-plating interface,is a precursor indicator of solder connection interfacial failure. The precursor is associated with vacancy accumulation and observation of Kirkendall voiding. Diffusion between the plating and the precipitation compounds leads to connection separation because the vacancy content of the plating can be up to twenty percent,and that vacancy content accumulates into area voids as the diffusion compounds grow. The diffusion compounds occur concurrent with,or subsequent to,the precipitation compounds. So the precipitation compounds are called first compounds. The diffusion compounds are called second compounds. The second (diffusion) compounds are stoichiometrically richer in the plating metal than are the first (precipitation) compounds. Technical examples show cross-sectional microstructures,and compound chemistry identifications,from the following solder-to-plating systems: tin-lead-to-gold,tin-lead-to-copper,indium-lead-to-gold,gold-germanium-to-nickel,tin-lead-to-iron-nickel and tin-lead-to-palladium. The influence of the first compounds on the mechanical properties of the solder connection can be characterized with predictability equations. However,the second compounds need to be avoided or minimized,by means of material selection (solder alloy,volume),plating design (metal,thickness,area) and processing parameters (plating,soldering). Lead-free solder connections to copper and iron-nickel finishes indicate qualification testing is needed,for lead-free solder alloys,showing their failure precursor compounds and voids are minimized.

Printed circuit assemblies have become more susceptible to a failure mode known as “pad cratering” due to the implementation of several material restrictions. Pad cratering is defined as mechanically-induced fracture between the copper pad/trace and printed circuit board (PCB)laminate. If left undetected during manufacturing,pad cratering can significantly reduce the reliable life of electronic products. The industry needs a fast,precise,non-destructive method to assess pad cratering,as it increasingly moves toward thinner,more mobile products. There are several methods being used in the electronics industry,both destructive and non-destructive,but all have significant limitations. Acoustic emission detection is a broad-area,non-destructive technique that has the potential to detect solder joint fractures. Passive acoustic emission detection (AED) records the sound waves emitted by fracture events during structural loading. This technique typically employs an array of piezoelectric transducers to measure sound waves at the surface; the location of the fracture event is calculated using the positions of the sensors,the time delay between the arrival of the events at the sensors,and the sonic velocity through the medium. This article discusses the development work performed to date by the authors in both transient bend and shock. The general test and data analysis methods are discussed. Transient bend and shock tests,results,and validation are described. Finally,further potential for the application of these methods to the electronics industryIPC-9709are presented.

Printed Circuit Board (PCB) weave texture and weave exposure are conditions that may appear similar if appropriate inspection techniques are not applied in a manner that can differentiate between the two. Weave texture is an area where the glass bundles of the PCB are visible beneath the intact resin of the PCB surface. Weave exposure is when there are openings in the resin of the surface layer of the PCB that expose the glass fiber bundles. Either condition is generally acceptable per MIL-PRF-31032/1 or IPC 6012 (Class 1 &2),as long as 1) exposed or disrupted reinforcement fibers on the horizontal surface of the PCB do not bridge conductors,and 2) the minimum conductor spacing is not violated due to the condition. The objectives of this paper are to describe and provide a summary of methods,approaches and techniques engaged in determining whether the functional performance of the printed wiring assemblies (PWAs) would be impacted by the condition found in a recent case history of weave exposure. Due to solder mask hiding the condition on the majority of the PCBs surface,it was initially thought the condition was weave texture. Some of the PCBs were then built into PWAs. Later it was determined that weave exposure was the condition,(with some weave texture).Due to the risks posed by this type of issue,including contamination and Conductive Anodic Filament (CAF) growth,a variety of techniques were utilized to evaluate the issue and determine the viability of using impacted PWAs. These techniques included,but were not limited to: visual examinations,PCB cross-section analysis,acoustic microscopy,scanning electronic microscope (SEM) evaluation with Energy Dispersive Spectroscopy (EDS),dielectric breakdown testing,Conductive Anodic Filament (CAF) testing,and Ion Chromatography testing. This paper provides a structured and methodical approach to determine the impact of weave exposure. The techniques described below may be utilized as a guideline for others facing a similar predicament to determine final acceptability of the product.

Reliable operation of electronics at higher temperatures requires a combination of performance improvements in components,interconnects and substrates. Ceramic based substrate options can be costly,heavy and prone to mechanical damage. Printed circuit board (PCB) options are restricted to lower working temperatures of the organic resins and degradation of their conductive tracks. A collaborative research programme between project partners has successfully developed innovative materials specifically designed to offer protection to organic PCBs and interconnects allowing them to operate at higher temperatures or for longer durations. Currently,the operation of electronic assemblies at higher temperatures is limited by the ability of copper clad PCBs to maintain circuit integrity. The project has developed a coating material which when applied to printed circuit assemblies (PCAs) makes them more suitable for operating at temperatures above 200oC.This paper summarises the work undertaken by the authors to develop and better understand the performance enhancements produced by these materials. The project brought together a materials supplier,an end-user and are search technology organization to jointly develop,test and implement the solution based on silicone coating materials. This paper focuses on the testing and materials evaluation undertaken to determine the long-term performance of these alternative materials in harsh environments. Details of the electrical performance of component and PCB interconnects between the substrates and components during the test regimes are given as well as the degradation mechanisms experienced in unprotected PCAs. The manufacturing process is outlined including details of the test vehicles utilised. Details of the test methodology used and comparable results for coated and uncoated systems will be given. The results show a significant improvement of mean-time-before-failure (MTBF) for coated PCAs and PCBs compared to uncoated samples. The primary performance improvement is shown to be reduction in the oxidation rate of copper in both the inner and outer layers of copper tracking in the multilayer structures.

The electronics industry could benefit greatly from low cost,easy to apply coatings that can be applied to almost any PCBA surface in order to provide effective and practical water (damage) resistance. In an effort to understand the relationship between the relative costs and benefits of the many varied approaches and materials,we have chosen to focus on state of the art,off the shelf,sprayable and dippable materials and compare them to one another as well as to the industry benchmark of poly(p-xylylene) polymer. According to suppliers,there have been some advancements in materials and techniques but the nature of these improvements as well as the specific formulations of the various materials is a closely guarded secret. Basic compositions and process specifics are given. Among the materials tested,there are two different approaches. One uses a very thin layer of material (as a continuous coating) and the other uses tiny “nano” particles to increase the surface energy of the treated surface in order to prevent water from condensing on the surface. In both cases,water and moisture may be present,but,in theory,they are prevented from wetting the surface. On the “coating” side,according to some suppliers,there have been changes (for example) to the cross-linking properties of polymers to enable a better (more rugged) barrier. On the nano-particle side,smaller and more effective particle materials have been developed. This work is an update/addendum to our prior work [1] with several new and “improved” sprayable/dippable water resistant nano-coatings tested. We conducted Insulation Resistance measurements and other tests/measurements including: Contact Angle,IPC-TM-650,test method 2.6.3.4,85/85,and Salt water exposure and present our findings.

In restricted-space applications,flexible PCBs must be able to fold with especially small bend radii. This in turn requires the return planes associated with microstrip and stripline transmission lines be cross-hatched. But the process of cross-hatching the return planes can significantly degrade the performance of these transmission lines. This paper shows examples of how the cross-hatching the ground plane introduces signal distortion and how changing the size,shape and orientation of the cross-hatch pattern can reduce some of the distortion.

Ultra-fine flexible circuitry has been more and more applied in electronic devices due to their fast innovation and the increasing demand on miniaturization,light weight and flexibility in some cases. These devices range from personal electronics to medical instruments,including smart phones,tablets,ultra-thin or/and convertible laptops,wear-able electronics,flexible connecting parts and antennas in all other types. In addition to their flexibility and light-weight advantages,flexible circuits need to incorporate ultra-fine features,maintain good signal integrity at high frequency transmission,and guarantee long-term use with good stability under heat-accumulated conditions. To meet such high requirements,polyimide (PI) has been the most widely used dielectric substrate material due to its very good electronic,physical and chemical properties. It has low Dk and Df to support high frequency signal transmission; low CT E,high Tg and Td to maintain good shape and size stability,thermal stability and processing ability; good chemical resistance,low moisture but good UV absorption. However,due to the superior properties above,it is generally difficult to obtain good PI-plating adhesion on the very smooth PI substrate,which is also required for good signal integrity in the ultra-fine circuitry. Even more challenging is to maintain the plating-PI adhesion at a certain high level after continuous exposure in a high temperature environment. To meet the demand,the company developed a semi-additive process (SAP-FLEX),which was tailored for different kinds of PI films widely used in the current market of the ultra-fine flexible circuitry. Using SAP-FLEX,the PI surface not only maintained a Ra lower than 27n m,but also consistently achieved a uniform initial peel strength from 715 to more than 2055 gf/cm on variant PI substrates. After a 7-day continuous baking test at 150oC,the peel strength can be maintained from 465 to more than 1287 gf/cm. This paper will discuss the SAP-FLEX process flow; its performance on different kinds of PI films; its processing window and the bath life of the adhesion promoter; and its process capability using Six-Sigma tools.

Any company that designs PCBAs that has gone through the throws of an acquisition,CAD tool change or even an EMS company with a varied customer base has to deal with more than one EDA tool and library. Many questions arise. How can the data be managed and re-used so parts built and validated in one tool can be leveraged for future designs in any tools available? How can leaders manage a global library team,share work between teams,monitor and prioritize work based on current status information? This paper will illustrate how multiple libraries can be designed to accommodate a variety of tool flows,and demonstrate a custom tool developed to control the library creation process as well as track revisions that are made to library models. The tracking,history,datasheets,supporting data and communication of this information is also managed within this browser based tool. Many CAD vendors offer specific solutions that are aligned to their tool sets. This solution is independent of any EDA vendor. This web-based tool also provides functionality that allows a global library team to seamlessly share work with workflows designed for custom part creation processes.

During the design of printed wiring boards,our engineers exchange files between the MCAD and ECAD tools in order to synchronize boards and to validate the fulfillment of design requirements. Because numerous iterations of “design then check” involve the generation and then transfer of two types of data exchange format files,and because file management,and therefore configuration control,was mostly absent,this activity was identified as prime for process improvement. Therefore,a custom application was developed to add automation and configuration control to the interoperations between our MCAD and ECAD systems. For the MCAD capability,a vendor supplied programming language application was developed to create new menu items which allow users to skip most of the menu picks previously required to import and export files. In addition,the program supports the automatic identification and tagging of geometric elements such as board outline,keep-outs and coordinate systems with appropriate data exchange attribute types. The ECAD vendor’s Application Programming Interface (API) was used to create new menu items in the ECAD tool that allow users to import and export files with pre-set standard options,instead of having to set dozens of options and layers manually. Utilization of our application allows our mechanical and electrical engineers to focus on design rather than the mechanics of generating,transferring and controlling files,thus trimming valuable time from the printed wiring board design process. This paper will include a process overview including background,use cases,development,and implementation process and cycle time savings.

Electronic component end-of-life (EOL) and declining prices are more problematic to industrial than consumer electronic products. Industrial electronic products typically have long product lifecycles. 10 years,15 years and up to 20 years are common. Declining component prices make older products less competitive than newer ones. Component EOL causes production disruptions. The number of components announced for EOL has been on the rise (figure 1). Three options are often employed to mitigate the risks: making a last-time-buy (LTB),using new product introduction (NPI) to replace the old one,redesigning an existing PCBA with the EOL and high-cost components replaced. While none of these options are perfect,redesign provides a balance among development efforts,mitigating EOL impacts,and reducing the product cost2. In this paper,we will present a collaborative approach to redesign in an environment where the internal funding and resources are limited.