This paper introduces line confocal technology that was recently developed to characterize 3D features of various surface and material types at sub-micron resolution. It enables automatic microtopographic 3D imaging of challenging objects that are difficult or impossible to scan with traditional methods,such as machine vision or laser triangulation. Examples of well-suited applications for line confocal technology include glossy,mirror-like,transparent and multi-layered surfaces made of metals (connector pins,conductor traces,solder bumps etc.),polymers (adhesives,enclosures,coatings,etc.),ceramics (components,substrates,etc.) and glass (display panels,etc.). Line confocal sensors operate at high speed and can be used to scan fast-moving surfaces in real-time as well as stationary product samples in the laboratory. The operational principle of the line confocal method and its strengths and limitations are discussed. Three metrology applications for the technology in electronics product manufacturing are examined: 1. 3D imaging of etched PCBs for micro-etched copper surface roughness and cross-sectional profile and width of etched traces/pads. 2. Thickness,width and surface roughness measurement of conductive ink features and substrates in printed electronics applications. 3. 3D imaging of adhesive dots and lines for shape,dimensions and volume in PCB and product assembly applications.

Both the number and the variants of Ball Grid Array packages (BGAs) are tending to increase on network Printed Board Assemblies (PBAs)with sizes ranging from a few mm die size Wafer Level Packages (WLPs) with low ball count up to large multi-die System-in-Package (SiP) BGAs with 60-70 mm side lengths and thousands of I/Os.
One big challenge,especially for large BGAs,SiPs and for thin fine-pitch BGA assemblies,is the dynamic warpage during the reflow soldering process. This warpage could lead to solder balls losing contact with the solder paste and its flux during parts of the soldering process and this may result in solder joints with irregular shapes,indicating poor or no coalescence between the added solder and the BGA balls. This defect is called Head-on-Pillow (HoP) and is a failure type that is difficult to determine.
In this study,x-ray inspection was used as a first step to find deliberately induced HoP defects,followed by pry-off of the BGAs to verify HoP defects and fault detection correlation between the two methods. The result clearly shows that many of the solder joints classified as HoP defects in the x-ray analysis have no evidence at all of HoP after pry-off. This illustrates the difficulty of determining where to draw the line between pass and fail for HoP defects when using x-ray inspection.

Voiding in bottom termination components (BTCs) like QFNs and LGAs have become quote the hot topic in the SMT industry. Surprisingly,one type of BTC component that is observed to have excessive amounts of voiding is the D-PAK. One would think that a component with leads located on only one side would mitigate flux entrapment and allow outgassing to escape more easily from beneath the component,as compared to other BTCs where the component is affixed to the PCB on two or more sides. However,the exact opposite has been observed in most cases. This study looks at an analysis of why a D-PAK exhibits more voiding than other types of BTCs. Voiding results based on an analysis of several process variables,such as adding weights to the tops of D-PAKs and cutting off the leads of the D-PAKs,will give insight into the physics behind D-PAK voiding,and provide an answer to the root cause to provide more insight on how to remedy the phenomenon.

The demand to produce smaller electronic devices and products to meet the needs of consumer electronic applications has resulted in thinner ball grid array (BGA) packages with finer pitches. Due to the z- height constraints of BGA packages,having a recess-in-motherboard (RiMB),where a recess is formed within the motherboard,allows for the placement of larger passive components on the land side of the BGA package. In this work,we evaluated: (i) the capabilities of three different suppliers to manufacture RiMB,(ii) three different metrologies to measure recess depths accurately,and (iii) the typical contour of a recess. There are different technologies to form recesses (i.e. laser versus mechanical routing),and this work found that there are differences in the process capabilities among suppliers,which can cause variation in the recess depths between RiMB manufactured by different suppliers. For the laser routed boards,the normalized variability plot comparing all three suppliers showed that Supplier B had the tightest range,but manufactured recesses on average were 23.4 µm below their specified target depth,resulting in shallower recess depths. Supplier C had the greatest variability and had quality issues where some of the recess depths exceeded the specified four sigma design requirement. Supplier A showed the best depth control and improved their depth accuracy from Lot 1 to Lot 2. For the mechanical routed RiMB manufactured by Supplier A,it was found that the mean recess depth was 162.0 µm ±12.6 µm. Due to the great variability and difficulty to control recess depths using mechanical routing,no further RiMB builds were pursued in this study using this manufacturing method. The metrology study found that the recess depths measured at room temperature using both an optical coordinate measuring machine (OCMM),and cross-sections were within 10 µm of those measured by the ‘Golden Metrology’,thus making them viable metrologies to accurately measure recess depths. Lastly,this work found that the general contour of the recess had the deepest depths at the inner edges of the recess,while the shallowest depths tended to be in the center of the recess.

In this era of electronics miniaturization,high yield and low cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate,the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µm,whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade,the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has createdunique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology,the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity,trace/via top planarity,which measures how flat the top of the traces and vias area few major features. This is especially important in multilayer processing,as nonuniformity on a lower layer can be transferred to successive layers,disrupting the device design with catastrophic consequences such as short circuits. Additionally,a non-planar surface could also result in signal transmission loss by distortion of the connecting points,like vias and traces. Therefore,plating solutions that provide a uniform,planar profile without any special post treatment are quite desirable.
Here we discuss innovative additive packages for direct-current copper electroplating specifically for IC substrates with capabilities such as embedded trench fill and simultaneous through hole plating and via filling with enhanced pattern plate.
These new solutions not only offer better trace profile,but also deliver via fill and through hole plating. Here we describe two electrolytic copper plating processes,the selection of which could be based on the via size and the dimple requirements of the application. Process I offers great via fill for deeper vias up to 80 – 120 µm diameter and 50 – 100 µm deep. Process II is more suitable for shallow smaller vias 50 – 75 µm diameter and 30 – 50 µm deep. In this paper we show that these two processes provide excellent surface uniformity and trace profile while also providing via filling and through hole plating capabilities when controlled within given parameters. Process optimization and thermal and physical characterization of the metallization is also presented.

The electronics industry is further progressing in terms of smaller,faster,smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades.
There are 4 main drivers which forced the chemical supply industry to introduce new electrolytic copper processes with the new feature of “filling” capability over the years. The 1st driver is the continuous miniaturization of electronics. The first blind microvias were introduced with HDI technology in the late 1980s and early 1990s. In 1996,the IC Substrate market started to fill the micro vias. “Plugging” technologies were introduced in order to stack the micro vias to save space or to create “via in Pad” structures. This “plugging” technology with conductive paste was very expensive because of the additional process steps required.
Today copper filled microvias are the standard for almost all HDI PCB manufacturers. The 2nd driver is the thermal management on a substrate. Solutions were needed to integrate features with high thermal conductivity to manage the heat transfer on the substrates from one side to the other in order to minimize hot spots on the electronic devices over a lifetime. The higher the chip performance is,the more it tends to generate local heat-spots resulting in an early loss of the electronics in the field. The reason for this is the degeneration of various materials at these local hot spots.
Meanwhile the complete copper filled through holes was realized in 2006,by bridge plating or X -plating technology. Nowadays,completely copper filled through hole structures are at the leading edge of technology for thermal via structures because copper has almost the best thermal conductivity and it has to be plated nonetheless. The 3rd driver is the signal frequency. Electronic signals in an electronic package or inside of a PCB are increasing over time and continue to do so. Stacked microvias and fan-out vias are becoming more and more of a disadvantage for the transmission of high frequency signals,due to the fact of creating resistances at high frequencies. Therefore,the push of high frequency applications further increased the demand for technologies like copper filled through holes.
The 4th driver especially for through hole filling,is the quality-yield aspect. The alternatives for electroplated copper filled through holes,requires many additional process steps,or new materials such as plugging pastes. Each of these additional process steps or materials introduces a variety of risks and manufacturing problems resulting in lower yield. Therefore the “one step” solution to fill through holes with copper is the preferred solution,without introducing new materials into the PCB. This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes,microvias and other copper plated structures on PCBs. The paper will contain aspect ratios,dimensions and results of plated through holes used today in high volume manufacturing for microvia and through hole filling with electroplated copper. Furthermore,it will also show feasibility studies of new electroplated structures for future applications such as copper pillar plating on IC-substrates.