A Rapidly Changing Supply Chain Landscape
Brian Swiggett, Managing Partner, Prismark
Smartphones, tablet computers and automotive electronics alone accounted for more than one third of all electronics systems value produced in 2013, up from only 13% five years ago. These markets combine high volume production, significant competitive cost pressure, and leading edge IC and sensor packaging requirements. With continuing market growth and device and systems design change, packaging and manufacturing engineers will be forced to adapt to an ever increasing set of challenges. The emerging "Internet of Things" will also drive significant volumes of low-cost wireless modules and sensors that adapt technologies spawned initially within the mobile and automotive sectors. The electronics industry has transitioned from the days of technology development leadership driven by infrastructure applications in computing and telecommunications, to an environment that demands creative, low-cost, high-performance solutions serving high-volume consumer-facing markets. At the same time, the rise of fabless IC and EMS/ODM manufacturers is changing where manufacturing innovation is ultimately taking place, and this too has important implications for the future.
This presentation will review key market and industry structural changes that are reshaping the supply chain, and highlight important device and packaging trends within mobile and automotive IC and sensor packaging. All companies are being challenged by the inherent growth of small form factor SMT and array packages, flip chip and WL-CSP, embedded components, modules and MEMs sensors, and ultimately 3D-TSV implementation. The need to often launch these emerging technologies first within high-volume cost sensitive markets is changing how the electronics industry manages technology and manufacturing innovation.
Packaging Technologies and Challenges on using fine pitch Cu-Pillar
MJ Lee, PE, Altera
As copper (Cu) bump technology becomes more mature, it is gradually taking the place of the conventional solder base bump in flip chip interconnections. Especially, micro-bump using Cu-pillar bump has already become essential platform technology for devices requiring finer bump pitch less than 100µm down to 40~20µm. Several motivations that Cu bump brings over solder bump are the fine pitch scaling capability in packaging process, superiority of mechanical endurance and electrical performance.
Although the baseline packaging technologies using Cu bump for around 50µm bump pitch and smaller than 100mm2 chip size has been in high volume production for many years, there are still many areas need further development to expand the technology envelop to finer pitch application and larger chip size i.e. <50µm multi-tier bump pad with up to 400~600mm2 die size.
Comprehensive experimentation have been conducted to get optimum Cu pillar structure, package substrate design, metal finish, thermal compression bonding process and underfill material for finer pitch but larger chip size packaging. This presentation will discuss about the technical findings and recommendation based on the lessons learned from the series of experimentation, including remaining challenges for achieving larger scale high density chip-on-substrate application in future.
Memory Platform Roadmap Trends and Challenges
Tom Gregorich, VP, Micron
More information coming soon.
Product Foundry - Accelerating Product Innovation through Platform Reuse
Dr. Erik Volkerink, Chief Technology Officer, Flextronics
It’s a Smart connected world – smart phones, smart energy, smart appliances, smart home, smart cars, smart health, and smart clothes. The confluence of new disruptive technologies in Human Machine Interfacing, Connectivity, Sensors & Actuators, Power & Battery Management, Computing and Materials is not only changing product design, it is changing the very fabric of products we use and envision through integration of digital intelligence.
Smart products are adaptive, pro-active, location aware, business aware, personalized, ubiquitous, and capable of interfacing with their environment with ease. This has led to a rapid increase in product development complexity that far outpaces development productivity, and has created increased pressure on new product development and introduction teams. Electronic product development systems need to keep up with this rapid innovation by improving processes, flows and tools to meet these challenges.
Packaging and Integration Trends in the Mobile Industry – Challenges and Need for Innovations
Dr. Urmi Ray, Qualcomm Technologies Inc.
The last decade has seen an exponential growth in the mobile phone and computing industry. The emergence of smartphones and the ever growing demand of packing more and more features and functionality by the consumers have rapidly driven innovations in advanced packaging and integration. Smart integration at reasonable cost is a key to driving advanced functionality to mass market quickly.
This talk will provide an overview of the latest trends in the mobile and wireless industries, with examples of architectural platforms, several disruptive technology platforms as well as evolutionary trends towards integration and miniaturization. Some key focus areas for industry innovation and collaboration include:
- Impact of SMT processes for new packages – need for “optimization”
- Package/board interaction issues- especially for thin packages
- New standards for characterizing the reliability impacts (e.g., Board Level Reliability and Temp Cycle)
Technology development challenges include tools, materials, infrastructure, reliability and many more. Several key challenges must be overcome before these integrations can be realized. In addition to lowering cost, increasingly complex tradeoffs, such as architectural partitioning, cost-performance-thermal, Chip-Package Interaction (CPI) must be managed. Electrical noise coupling, thermal interaction, and mechanical stress effects require multiphysics simulation and an infrastructure to support “design for X” across multiple domains. Tools, models, methodologies, materials, structural constructs, and experimental results are needed to ensure quality, yield and reliability.
Dr. Urmi Ray is a Principal Engineer in the Qualcomm Advanced Technologies group. She has been the technology lead in several forward looking programs in 3-D and 2.5-D, with particular focus on low cost packaging for mobile industry. She joined Qualcomm in 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability for a diverse set of product portfolios, including consumer products to high reliability telecommunications projects. She is currently active in the 3-D technology area. She has a Ph.D. from Columbia University (New York City).
IC Packaging Roadmap Challenges, Trends an Opportunities
Dr. Mike Ma, Siliconware Precision Industries Co., Ltd (SPIL)
From the mobile computing era trending into ubiquitous computing era, IC packaging technology is driven by the need of continuous form factor reduction in three dimensions, shortening and optimizing interconnects for enhancing system performance; and with the challenge to maintain the cost structure with all the enabling new technologies.
In order to support the performance, cost, and form factor demands, IC process technologies such as stealth dicing, thermal compression bonding, temporary carrier bonding / debonding for thin wafer processing are developed by the materials and equipment eco-system and are evaluated by OSATs. Selection of new technologies to be included in development portfolio will be discussed. Dr Ma will further provide updates on these technologies such as fine pitch wiring, TSV based 2.5DIC/3DIC, large panel format Fan Out (FO) packaging, and other innovative packaging solutions.
The Growth of Wafer-level Fabricated Package Interconnections
Glenn Rinne, Vice President R&D, Amkor Technology
Since the 1961 invention of flip chip by Eric Bloch at IBM to the present day 2.5D interposer package, the maximum number of solder bump interconnections per die has increased by five orders of magnitude. As our industry contemplates the next big thing in microelectronic packaging it can be instructive to review our progress thus far. A brief review of the beginnings of bump interconnection technology will be provided by Glenn Rinne who has been in the center of changes, to remind us of the many challenges and advantages of solder bump technology remaining with us today. Modern interconnection requirements are pushing bump technology into new territory where new challenges await. Using the historical perspective to extrapolate our future trajectory, some possible paths forward will be discussed.
Printed Circuit Fabrication: Trends and Continuous Challenges
Dr. Craig Davidson, Vice President Engineering & Technology, Viasystems Group Inc.
As a result of the density requirements, features such as circuit trace widths, via diameters, and dielectric thicknesses continue to decrease while PCB layer counts continue to increase. Faster circuit speeds have led to an increasing number of new high performance materials in need of extensive reliability testing and characterization of design interactions. Distribution of higher power and dissipating more heat are leading to novel and complex designs employing very heavy copper (e.g. 3-12 oz) and embedded or press fit heat sinks and heat spreaders. Fabrication of printed circuits relies on four monument processes that are fundamental to circuit definition: drilling, imaging, plating, and etching. The implications of these trends for each of these monument processes will be discussed along with assessments of the reasonable limits of today’s conventional approaches to circuit fabrication.
Enabling the Internet of Things: Market Trends and Packaging Implications
Glenn G. Daves, Director of Packaging Solutions Development, Freescale Semiconductor, Inc.
We are in the midst of an explosion of internet-connected devices. Now numbered in the billions and expected to reach the trillions, the internet of things will inter-connect every conceivable function, process, and data stream. The implications of this trend are far-reaching for the electronics industry. Some of the more important implications that relate to microelectronic packaging will be explored. In addition, the packaging building blocks and emerging technologies required to enable the Internet of Things will be examined using relevant examples.
Integrating Design, Interconnect Technology and Manufacturing Solutions to better serve the needs of High Performance Electronic Systems – How Do We Improve?
Dr. Sundar Kamath, Senior VP Corporate Technology, Sanmina Corp.
The ever-growing demand for higher bandwidth and faster streaming of data and video content in today’s wireless and optical networks, poses a renewed set of challenges for system designers and manufacturing engineers alike – tomorrow’s electronic systems must be lower cost, quicker to market, more reliable, deliver better performance, easier to deploy, consume less power, meet sustainability needs…and the list goes on. As the level of sub-system integration grows with each product cycle, interconnect density and performance become critical. Products that are sub-optimized for the integrated design and global manufacturing environment invariably face market launch issues. What does it take to achieve the optimum balance between product needs, design solutions, and manufacturing technology that can enable system level success in a timely manner? In his keynote speech at the 2014 Electronic System Technologies Conference and Exhibition, Dr Sundar Kamath will explore these issues and field-tested solutions in light of product level case studies.
State of Pb-free Solder Joint Reliability Overview
Dr. Vasu Vasudevan, Corporate Quality and Reliability, Intel Corp.
Newer generation smaller and thinner electronic packages with Pb-free solder and increasing I/O density demand accurate reliability prediction to be cost effective. Solder joint reliability (SJR) is the ability of solder joints to survive duty cycles in use environments for a given product life. SJR is assessed through temp cycle, shock and vibration testing. Temp cycle testing is an accelerated whereas shock and vibration testing are worst case event tests. The temperature range, dwell time, and number of cycles of the accelerated test are critical in estimating product life, in addition to the package type. For example, large ceramic BGA packages can show poor temp cycle performance in accelerated testing compared to flipchip BGA due to higher SJ strain.
With the Pb-free transition, numerous papers were published on SJR for various package types and compared with Sn/Pb solder. Solder fatigue combined with creep is responsible for the wear-out failure mechanism. To date, most Pb-free reliability models were based on temperature cycle testing, and Sn/Pb temp cycle models. Even though multiple reliability models exist in the literature, Norris Landezberg (N-L) model is the most commonly used for board level SJR prediction. Pb-free reliability concerns include the impact of temp cycle dwell time and high strain. Pb-free solder was expected to creep continuously and show a poor field reliability performance, although it performed well in high temperature cycle tests.
Literature data indicate accelerated temperature cycle performance of Pb-free solder is better than SnPb for low strain components, whereas temp cycle performance is lower for high strain components (such as large ceramic BGA). However, recent use condition regime temperature cycle testing of large strain components shows lead free is more reliable compared to SnPb. In high reliability applications such as aerospace and military, customers have concerns about Pb-free reliability. During the last decade, there have been new learnings and those concerns were addressed through extensive data collection. Our study long dwell time study at Intel Corporation shows that Pb-free is more reliable compared to SnPb solder. Literature data in the use condition regime tests show higher temp cycle performance for Pb-free solder compared to Sn/Pb even for large ceramic BGA.
Literature and Intel data have been used to show Pb-free is more reliable than Sn/Pb solder. Numerous Pb-free reliability models both empirical (N-L variation) and FEA based models will be reviewed and recent Pb-free reliability learnings will be shared. Pb-free reliability model development and correlation to use condition will be discussed based on near use condition regime testing. Power cycle results also will be shared to show the Pb-free filed reliability margin. Additionally end of life product teardown results will be shared to estimate the use condition damage. DOE results for end of life + power cycle and end of life + temp cycle results will be shared for product life. Field product life estimate will be reviewed based on use condition and PC test damage estimate. The results show that the consumer products have a very high field life about 4 to 10X of designed life. The impact of use condition based product filed life estimation for cost effective options will be reviewed. The results to date show that the initial Pb-free reliability estimation was conservative and Pb-free solder is more reliable than Sn/Pb solder.
The Future of Solder Joint Encapsulant Adhesives
Dr. Wusheng Yin, President, Yincae Advanced Materials
Solder joint encapsulant adhesives have been successfully used for many years by major electronics manufacturers to enhance the strength of solder joints. These products have proven to strengthen solder joints 5-10x over traditional methods, and have greatly improved thermal cycling during the soldering process as well as the drop performance in the finished products. The use of solder joint encapsulant adhesives can eliminate the need for underfill materials and the underfill process altogether, thus simplifying rework which results in a lower cost of ownership. Solder joint strength, however continues to be a problematic issue with increased package on package and system on package miniaturization.
Research tests were performed to compare the solder joint strength using flux in nitrogen reflow process versus solder joint encapsulant in air reflow process. Using flux in nitrogen the top PoP had a solder joint height of 11.85 mil with 0.9 mil warpage and 5.25% solder voids. In comparison, using solder joint encapsulant in air, the PoP had a solder joint height of 11.33 mil with 0.8 mil warpage and 2.93% solder voids. The pull strength of solder joint was 71 N using flux compared to 352 N using the solder joint encapsulant. The first thermal cycling failure was increased from 495 cycles using underfill to around 5000 cycles using the solder joint encapsulant. From the data it is evident that solder joint encapsulant provides a very promising solution for solder joint strength in the evolution of miniaturized electronic packaging. In this presentation we are going to discuss the details and future of solder joint encapsulant adhesives.
Knowledge Based Qualification: Enabling Future Packaging Solutions and Customer Design
Dr Milena Vujosevic, Principal Engineer and Q&R Component and Modeling Manager, Corporate Quality and Reliability, Intel Corp.
During last decade we have been witnessing rapid proliferation of semiconductor components in diverse market segments. This is a consequence of Moore’s law driven improved performance of semiconductor devices and their smaller form factors. Semiconductor components are present in a wide variety of applications: from warehouse to wearables and from stand-alone applications to always connected. This in turn results in a variety of different use conditions they are exposed to and in a variety of different expectations users have for their performance. This has important practical applications for qualification of semiconductor components, including the ball grid arrays (BGAs).
Traditionally used standards based qualifications are based on assessing the capability of the component to pass a specific set of stress tests. However, passing this standards based tests does not necessarily guarantee that the component will meet the required reliability life in the field. It also might results in a component having capability much larger then needed and thus being more expensive. This represents a very important concern for component manufacturers and their customers who all want to have cost effective products that would have adequate life under use condition and meet the expectation of the end user.
Knowledge based qualification is proposed as an alternative to standards based qualification with the objective to generate more realistic designs that would meet end-user expectations. In knowledge based qualification, the accelerated test is defined in a way that passing the test will assure that component will meet its use condition requirement. The key components of knowledge based qualifications are: knowledge of the use conditions/customer expectation, knowledge of failure modes, comprehension of physics of failure metrics and availability of validated predictive methods and tools
The talk will cover Intel approach to knowledge based qualification of BGAs. It will describe methodologies used to comprehend customers systems and quantify use conditions. Special focus will be on explaining how use conditions are translated into the qualification requirement. Related to this, the essential role of physics based metrics will be discussed at length, and why and how thermo-mechanical modeling is used to access these metrics. It will be shown that when qualification requirement are knowledge based they have to be form factor depended which is opposite from standards based requirements that are independent of form factor. As a consequence the resulting components have more realistic design that in many cases results in smaller and less costly packages and more available space on the board. Most important is that in order to meet challenges of future BGA technologies and customer expectations it is essential that definition of requirement be based on thorough understanding of use condition and physics. Knowledge based qualification provides a sound technical framework for such an approach.
Peridynamics for Simulation of Damage in Electronic Packages
Dr. Erdogan Madenci,
Aerospace and Mechanical Engineering Department,
University of Arizona, Tucson, AZ, USA
Simulation of damage initiation and its subsequent propagation in electronic packages is still a major challenge despite the development of many important concepts. The main difficulty lies in the mathematical formulation of the classical continuum mechanics. It breaks down whenever a discontinuity appears in the material. Also, there is no internal length parameter distinguishing different length scales. Although the classical continuum theory is incapable of distinguishing among different scales, it can capture certain failure processes, and can be applied to a wide range of engineering problems, especially by employing the Finite Element Method (FEM). The FEM is robust in particular for determining stress fields, and it is also exceptionally suitable for modeling structures possessing complex geometries and different materials under general loading conditions. However, its governing equations are derived based on the classical continuum mechanics, and it also suffers from the presence of undefined spatial derivatives of displacements at crack tips or along crack surfaces.
Alternatively, a nonlocal continuum theory referred to as peridynamic theory eliminates these shortcomings, and provides the ability to address multiphysics and multiscale failure prediction in a common framework. The theory uses spatial integral equations that can be applied to a discontinuity. The peridynamic governing equations are defined at fracture surfaces; additionally, material damage is part of the peridynamic constitutive laws. These attributes permit damage initiation and propagation to be modeled, with arbitrary paths, without the need for an external criteria. This presentation will describe the peridynamic theory and demonstrate its predictive capability by considering electronic packages subjected to complex loading conditions in the presence of coupled fields. It will also include a brief description of ongoing work for further advancement and different applications of peridynamics.
Opportunities and Challenges for Advanced Packaging to Realize Increased Value Add with 2.5/3D
Paul Enquist, CTO/V.P. R&D, Ziptronix, Inc.
The ability of wafer foundry CMOS scaling to continue delivering required increases in functional density at reduced cost has become more difficult over the last few nodes due to a number of demanding challenges including lithography, transistor power/thermal performance, interconnect parasitics and foundry capital expenditure. The development of advanced packaging technologies over the last few years including TSVs, interposers, solder bump, copper pillar, temporary bond/debond, and thin die/wafer handling in conjunction with these foundry limitations has created an opportunity for substantial increases in functional density at lower cost to be enabled by 2.5/3D. Realizing the full potential of this opportunity will require a number of challenges to be overcome with regard to cost (e.g., interposers, TSVs, etc.) and scaling (e.g., bump/pillar pitch, TSVs, die thickness, etc.). This presentation will review the status of 2.5/3D technology and its adoption and identify opportunities and challenges that once realized and overcome will further enhance the value-add of advanced packaging suppliers in the supply chain. These opportunities and challenges center on achieving a significantly greater percentage of cost, interconnection, and form factor scaling value-add within the packaging portion of the supply chain that has previously been realized by CMOS wafer foundries.
Packaging Challenges for IOT and Wearables Products
Terrance (Terry) J. O'Shea, Fellow, Hewlett-Packard Company
Terrance (Terry) J. O'Shea, Ph.D. is newly appointed HP Fellow in the PPS CTO Office, where he is chartered with development of the Wearables and IOT Technologies for the next generation of HP products. With over 20 years' experience, O'Shea is considered a pioneer in the field of wireless sensor networks. In his current position, he is responsible for research and development of novel sensor-based technologies for a multitude of applications, creation of systems and system architectures, and new products in the aforementioned fields. Prioir to joining HP, Terry was a senior principal engineer in Intel Labs. He joined Intel Corporation in 1997 as a staff engineer, designing and developing the interface between the processor and chipset for the Pentium® II, Pentium® III and Pentium® 4 systems.
Dr. O'Shea has launched 5 different revenue and profit-producing wireless sensor based platforms as spinouts from Intel. One was launched on the NYSE floor in 2008 with the Prime Minister of Ireland, called SHIMMER-Research.com. O'Shea has been a PI or Co-PI on over $42M in grants from various organizations including Intel Research, Enterprise Ireland, Microsoft Research, National Science Foundation, and the National Institute of Health. During his tenure at Intel, O'Shea served on the faculty of the State University of New York at Buffalo and has co-authored two textbooks—most recently, Applications of Wireless Sensor Networks for Healthcare, published in 2009. He is the author of more than 80 other publications in electronic packaging, biomedical engineering, computer science, electrical engineering, sensor networks, sensing, and structural mechanics. His papers have been published in numerous IEEE symposia and in periodicals such as IEEE Electronic Packaging, Circuit World, Journal of Biomedical Materials Research, Geriatric Medicine, and Journal of Applied Physics. In addition, he holds 69 patients and another has 68 patent applications pending.
Prior to joining Intel, O'Shea was on the faculty of the University of Maryland. O'Shea holds a Ph.D. in engineering science from the University of Arizona and master's and bachelor's degrees in engineering mechanics from the University of Tennessee. Before he attended college he was in the 7th Special Forces Group Airborne at Fort Bragg, NC.