The Impact of Updates to J-STD-001

Boston, MA. - October 12, 2010 9:00 am to 5:00 pm

Toronto, ON, Canada - October 14, 2010 9:00 am to 5:00 pm

If you use J-STD 001, Requirements for Soldering of Electrical and Electronics Assemblies, as your basis for assembly and soldering requirements, this course is a must-attend. Revision E of this key industry document will feature changes that address constantly evolving solder technology. Taught by the chairman of the J-STD-001 Task Group, you will learn about specific requirement changes, and also learn the reasons behind them. A copy of the standard will be provided.

What You Will Learn:
How J-STD-001, Requirements for Soldering of Electrical and Electronics Assemblies Revision E, will impact:

• Materials (lead-free solder bath contamination limits)
• New hole-fill criteria
• New SMT termination styles
• Supplier flow-down
• Training for proficiency and rework
• Compatibility with other IPC documents such as IPC-A-610E

About the Instructor
Teresa Rowe is the director of quality for the logistics and technical services business unit of AAI. She is the chairman of the IPC task groups for J-STD-001, J-STD-001 Training and Repair Training (Technical) as well as the 5-22 Soldering Subcommittee.

A copy of the standard will be provided.

The Impact of Updates to IPC-A-610

Boston, MA. - October 13, 2010 9:00 am to 5:00 pm

Toronto, ON, Canada - October 15, 2010 9:00 am to 5:00 pm

IPC-A-610E reflects the industry’s use of process control by re-categorizing many conditions as either defects or process indicators. This workshop will discuss the specification from a common sense “show me” perspective for understanding and applying the new criteria. You will be able to assess the impact these new established requirements will have in your customer–supplier relationships. You will also learn the target conditions for all three classes of production and how target conditions differ from acceptable and defect conditions. This is a must for anyone who works with acceptability of printed circuit assemblies. A copy of the standard will be provided.

What You Will Learn:
Attendees will discover how IPC-610, Acceptability of Electronics Assemblies Revision E, will impact:

• Surface mount criteria: new component leads, BGA criteria and solder contact with component body
• Soldering connection requirements: wetting requirements, intrusive soldering and lead-free criteria
• Mechanical assembly
• Depanelization criteria
• Flex criteria
• Particulate matter criteria
• Cleanliness no-clean vs. clean
• Process control indicators: form, fit, function
• Component damage

About the Instructor
Constantino J. Gonzalez chairs the IPC Acceptability subcommittee and the IPC A-610 task group. Gonzalez has been chairman throughout all revisions of the standard and has extensive practical experience with the content. He is president of ACME Inc., an approved IPC training and certification center and consulting firm with services for the electronics assembly Industry.

A copy of the standard is included.

The Impact of Updates to IPC-A-600 and IPC-6012
Irvine, Calif. - June 8, 2010 9:00 am to 5:00 pm
The Atrium Hotel Orange County Airport

San Jose, Calif. - June 10, 2010 9:00 am to 5:00 pm
Wyndham San Jose

Discover drivers behind the revisions to IPC -6012C and its companion document, IPC-A-600H, Acceptability of Printed Circuit Boards. This workshop will dissect the new specifications to give you the practical knowledge you need to properly apply a performance specification for your product. Understand the engineering requirements behind the performance attributes specified in the IPC-6012, Qualification Performance Specification for Rigid Printed Boards. In addition, learn how to implement drawing notes to cover AABUS (As Agreed Between User Supplier) requirements to clearly communicate your engineering requirements. Copies of the standards will be provided.

What You Will Learn:
How IPC-6012C and IPC-A-600H impact:

• The fabrication processes behind the requirements
• Engineering performance drivers behind changes
• New copper cap plating requirements for filled vias
• Requirements for copper wrap plating
• New thermal stress methodologies
• Requirements for etchback and dielectric removal
• Requirements for laminate anomalies
• Supplemental requirements for space and military avionics
• Understanding frequency of lot inspection for product acceptance
• Requirements for new surface finishes such as electroless nickel/electroless palladium/immersion gold (ENEPIG), immersion tin and immersion silver
• Measles in printed boards — process indicator or defect condition?

About the Instructor
Don Dupriest is a member of the production technical excellence staff within Lockheed Martin Missiles and Fire Control. Don has more than 35 years experience in electronics manufacturing and is currently on the advanced manufacturing technology staff. A past recipient of the IPC President’s Award, a past chair and current member of the IPC Technical Activities Executive Committee, he has chaired the IPC D-30 Rigid Printed Board general committee and is current co-chair of the IPC D-35 Printed Board Storage and Handling Subcommittee.

A copy of the standard is included.

Lead-Free Assembly for High Yields and Reliability
San Jose, Calif. — June 22, 2010 9:00 am to 5:00 pm
Wyndham San Jose

With the advent of global environmental regulations, there is a need to develop a strategy for compliant electronic assembly with high yields and excellent reliability. This workshop will present such a strategy.

This course will briefly review global environmental regulations and how they affect the electronics assembler. The inputs for successful assembly: PWBs, components, and solder paste will be presented. We will spend considerable time discussing the various lead-free alloys and their effect on reliability. Assembly process optimization will be covered, emphasizing fine pitch stencil printing and reflow soldering. How to prevent “Head-in-Pillow,” voiding, “graping,” tombstoning and other process defects to assure high yields and good reliability will be discussed. The workshop will conclude with two successful RoHS compliant process implementations.

What You Will Learn:

• Current alloy systems in use — why and how they were chosen
• The reliability of different alloy systems
• Preferred printed board finishes for lead-free assembly
• Concerns with lead-free components
• Solder paste selection
• Best practices for setting up a RoHS compliant process
• How to prevent process defects
• The strategies of two successful process implementations

About the Instructor
Ronald C. Lasky, Ph.D., PE is an instructional professor and a Six Sigma master black belt Instructor at Thayer School of Engineering, Dartmouth College. Dr. Lasky serves as director of the Cook Engineering Design Center, and as a senior technologist at Indium Corporation of America. He has more than 30 years of experience in electronic and optoelectronic packaging, including work at IBM, Universal Instruments and Cookson. The author of five books, Dr. Lasky holds a doctorate in materials science.