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This comprehensive event is a thorough review of product verification at each level of the manufacturing process.
Industry experts will present testing methods and equipment with an emphasis on positioning to match customer expectations. There will be additional focus on:
- Strategies for Cost Reduction
- Cycle Time to Market
Time is money, and reducing time to market goes right to the bottom line. Rather than simply finding mistakes after the fact, real process improvement translates to improved yield. Get the research in your hands that will lead to process improvement!
This event saves time and energy for participants with a full range of strategies and equipment - all in one place. A structured framework for presentations adds value, allowing for for "apples to apples" comparisons: every speaker will answer the same questions, from a specific checklist created by the Program Committee.
This is a great opportunity to come up to speed on new applications of established technologies to the printed circuit board: environmental stress screening (ESS), infrared radiation (IR), ultrasound, and thermal imaging.
Setting the stage for the two-day technical conference is the "Future of Test and Inspection Protocols" workshop on Monday afternoon. concluding with supplier presentations on Wednesday and a facility tour, the IPC International Test and Inspection Technology Conference is critical for Engineering Managers and Test Engineers.
Location and Hotel Accommodations
Both the educational course and technical conference will take place at the Embassy Suites, 2885 Lakeside Drive, Santa Clara, California 95054. For reservations, please call +1 408-496-6400 and ask for the special IPC rate of $199 per night. Rate is subject to change after November 1, 2008. |
Future of Test and Inspection Protocols - Workshop
November 10, 2008
1:00 pm - 5:30 pm |
Dieter Bergman, IPC Director of Technology Transfer
Arden
Bjerkeli, ASSET InterTech, Inc.
Jack Fisher,
Interconnect Technology Analysis, Inc. |
A test plan is written, approved and then implemented to fulfill the validation process. Test development activities follow documented procedures. Processes have been refined to meet relevant standards.
This workshop will give you an overview on each of those test and inspection processes and how to assess proper test protocol strategies within your test and inspection process.
Topics to be covered
Testing Strategy Overview
Provides insight into the many different methods used for verification that the manufacturing process creates product at quality level demanded by the customer. Various techniques – and their pros and cons – will be discussed.
Understanding Electrical Test
Covers a range of opportunities for ensuring that items purchased or produced will function electrically. Basic methods and equipment usage information is provided to illustrate capability and testing cycle-time for each technique.
Boundary Scan 101
Illustrates basic principles of this test methodology, and how concepts must be built into the semiconductor package at time of die development. This section includes IC testing to ensure overall functionality.
Alternative Inspection Methods
Discusses non-electrical testing techniques used to verify product performance & quality assurance. Visual and X-Ray system technology processes are also addressed.
Test Protocol Risk Assessment
Promotes use of sampling plan techniques, and establishes risk level associated with potential on-conforming product escape. Reviews test strategy redundancy for full product testing coverage.
Who Will Benefit
Both manufacturing and test engineers from OEM and EMS companies of all sizes will gain a solid understanding of today's test and inspection technologies. The rules have changed, and test methodologies have become a collaborative activity between the end customer and the assembler. Cost is a major driver, as well as the need to verify quality and integrity of assemblies in NPI and prototype quantities. Quality control professionals and operations management will benefit as these new rules become an integral part of the manufacturing process. Suppliers of inspection and test equipment will contribute as well as benefit from this workshop.
Instructors
Dieter Bergman, IPC Director of Technology Transfer, has instructed PCB designers for more than two decades, and was instrumental in the development of the IPC-2221, as well as many other design-related IPC standards.
John T. (Jack) Fisher has been in the PCB industry for 35 years, having worked at both IBM and most recently at ITRI (Interconnect Technology Research Institute). While at IBM, Fisher held several senior management and staff positions in maintenance, manufacturing and engineering in both Endicott, N.Y. and Austin, TX. Fisher received IPC’s 1996 Chairman of the Board Award for his work to improve PCB interconnect technology and was elected to IPC's Hall of Fame in 2007.
Arden Bjerkeli, Director of Customer Applications Support, ASSET InterTech, has been involved in the electronics industry for over 20 years. At ASSET, Arden manages the engineering group that provides pre- and post-sales support, customer services, and customer training. Before joining the company, he held engineering management positions at Compaq, responsible for test strategy for desktop computers and server products. His R&D team provided the research that introduced new test methods and fixture innovations. |
We expect a strong turn-out for the tabletop display area during the conference breaks and lunch on November 11, 2008 and November 12, 2008. Don't miss out on this opportunity to reach your audience. For pricing information and a tabletop application click here(.pdf).
Tabletop Sponsors:
Media Sponsors
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Conference Agenda - November 11, 2008 |
| 8:30 am |
REGISTRATION |
| 9:00 am |
Supply-Chain Testing: What are Suppliers Doing?
Components
Joe Fjelstad, SiliconPipe, Inc. |
| 9: 30 am |
The Impact of Glass-to-Resin Ratio and Sample Construction on the CTE of a High Temperature Laminate
Silvio Bertling, Nelco |
| 10:00 am |
BREAK |
| 10:30 am |
PCB Manufacturing
Ron Rocha, Hunter Technology, Inc. |
| 12:00 pm |
LUNCH |
| 1:00 pm |
Non-destructive Techniques for Identifying Defects in BGA Joints: TDR, AXI, 2DX, and Cross-section/SEM Comparison
Zhen (Jane) Feng and Murad Kurwa, Flextronics |
| 1:45 pm |
Assembly Test and Inspection Methodologies
Rob Jukna, Jabil |
| 2:30 pm |
BREAK |
| 3:00 pm |
Closing Keynote: The Future of Testing-OEM Perspective
Steve Butkovich, Cisco |
| 5:00 pm |
ADJOURN |
Tour at Hunter Technology:
Hunter Technology has graciously agreed to host a tour after Tuesday’s conference sessions. This is for all registrants. Hunter Technology is located at 2941 Corvin Drive, Santa Clara, CA 95051-0705. Please join us in the lobby of the hotel at 5:30 p.m. We will make arrangements to get from the hotel to Hunter Technology. If you would like to attend and haven’t informed us yet, please call an IPC registration representative at 847-597-2861 or send an email to registration@ipc.org.
Welcome to Hunter Technology
A Trustworthy and Reliable Source of Advanced Electronic Manufacturing Services Including PCB Design, Fabrication & Assembly Services
Hunter Technology provides a full range of Electronic Manufacturing Services (EMS) including: Printed Circuit Board Design & Layout, PCB Fabrication, PCB Assembly, Contract Manufacturing, Test & Systems Integration. Hunter's high reliability new product introduction (NPI) center is located in the heart of the Silicon Valley. Hunter offers a fully integrated solution insuring you a competitive edge. Hunter's breadth of operations provide you with the ability to source everything from quick-turn prototypes to volume production directly from a single manufacturer. |
Conference Agenda - November 12, 2008
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| 8:00 am |
Keynote: Variation in Testing Strategies
Jack Fisher, Interconnect Technology Analysis
Inc.
Test and Inspection Equipment for the Future
The testing strategies and methods described in the preceding two days require equipment to keep pace with customer demands. This session will provide an overview from suppliers representing unique disciplines. In addition to technical presentations, displays will provide attendees with the opportunity to see new offerings and upgrades to existing equipment.
- Overall test strategy
- Stand-alone/complementary technologies
- Cost implications
- Cycle time and impact on time to market
|
| 8:30 am |
MDA Test
Floyd Conner, Test Research USA, Inc. (TRI) |
| 9:00 am |
Twilight of the In-Circuit Era
John VanNewkirk, CheckSum |
| 9:30 am |
Test Fixtures
Dan Gallant, ReMaTek |
| 10:00 am |
Getting the Most of Your In-Circuit Tester in a Limited Access Environment
Jack France, Agilent |
| 10:30 am |
BREAK |
| 10:45 am |
Flying Probe Test
Michael Casper , Seica, Inc. |
| 11:15 am |
Selecting the Perfect Switching System
Bill Green, Pickering Test |
| 11:45 am |
Boundary Scan
David Kalaidjian, Corelis, Inc. |
| 12:15 pm |
LUNCH |
| 1:30 pm |
Automatic Optical Inspection (AOI)
Martin Gershenson, Christopher Associates |
| 2:00 pm |
AXI (Automated X-Ray Inspection)
Carston Salewski, Viscom, Inc. |
| 2:30 pm |
Using IR Technology to Quickly and Accurately Detect Problems
Eric Hughes, Flir Systems |
| 3:00 pm |
New Techniques for More Effective Ess
Mike Silverman, Ops a la Carte, LLC |
| 3:30 pm |
Intro to AMI: Acoustic Micro Imaging Applications
Steven R. Martell, Sonoscan, Inc. |
| 4:00 pm |
ADJOURN |
| 5:00 pm |
TOUR - Viscom San Jose facility |
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IPC International Test and Inspection Technology Conference:
Meeting Customer Demands
November 10-12, 2008 - Santa Clara, California

Register before October 10, 2008 and save 10%
Register three individuals from your company at the same time
and receive the fourth registration FREE. Discount will apply to lowest cost registration.
(download PDF file of the registration form) |
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