DesignForAdvanced Packaging

Design for Advanced Packaging
Hosted by Tessera, Inc.
June 3-4, 2008 - San Jose, Calif.

As technology advances, electronic packaging has become more sophisticated and complex. Many of the new IC device families have more leads and a finer contact pitch than their predecessors or dissipate more heat dramatically, affecting the methodology used in board design and assembly. When adapting these families of component packages one must consider the physical attributes and tolerances of the component package, the board fabrication tolerances, the assembly process methodology and related machine placement accuracy.

Increased electronic functionality can be achieved through the development of more complex silicon integration. Unfortunately, that route generally requires a great deal of capital resources and time. For that reason, many manufacturers will rely heavily on more innovative package solutions, including solutions for integrating a number of already proven functional elements within a single-package outline described as Stacked Die Packaging. When adapting multiple die configurations, risk is minimized because each package becomes a fully tested subsystem that can be certified by the supplier before board or module level assembly.

The Design for Advanced Packaging workshop will cover many of the challenges and the risk associated with making the right decisions to adapt the newer component package innovations.

About Tessera, Inc.
Tessera is a leading provider of miniaturization technologies for the electronics industry. Tessera enables new levels of miniaturization and performance by applying its unique expertise in the electrical, thermal and mechanical properties of materials and interconnect. Tessera's technologies are widely adopted in high-growth markets, including consumer, computing, communications, medical and defense electronics. More than 10 million semiconductors worldwide incorporate Tessera's technology.

Tuesday June 3, 2008:

Design Considerations

Design considerations explores existing standards and evolving guidelines on Rigid, Flex boards and assemblies, pc cards, modules, embedded passives. In Addition other new technology intended to address tighter tolerances; greater electrical capabilities and increased product performance requirements are also discussed. The lectures include a discussion on CAD/CAM capability and data transfer.

Managing the SMT Packaging Strategy

After defining the SMT product application we will discuss the criteria for determining the end use environment and identifying assembly types and their complexity. In regard to assembly complexity, we will review the optional methodologies available and review the basic processes required for assembly the several mixed technology product variations.

Pitch Influence

The discussion on pitch reviews the methods needed to interconnect the various portions of the semiconductor device. Since electronic assemblies are composed of many different parts the methods of trying to establish a consistent and organized technique for having the parts and their IO’s fit into a uniform attachment strategy are reviewed. As component manufacturers continue to evolve new parts, without consideration for the next level of packaging, solutions that make pitch less important will be part of the concepts that each designer needs to explore.

I/C Packaging Technology

IC package evolution will be discussed along with an overview of the primary IC package variations in wide use today. Detailed information for IC package standards will be reviewed including plastic lead-frame packaging, SON and QFN packaging and array packaged ICs. In this session we will study the JEDEC design guidelines for a wide spectrum of array packaged IC that includes, plastic BGA, Chip-scale FBGA, Die Size DSBGA, wafer level packaging (WLP) and new package-on-package innovations.

Mounting Substrates

The subject of mounting substrates is on everyone’s agenda especially since the new attachment alloys used for assembly require a more robust laminate be used for the component interposer, any application specific module or the product board. The various options are discussed and include some materials that are known for their thermal properties as well as the new descriptions intended to define those materials that can meet the new alloy assembly temperatures. Other related materials, such as solder mask and legend are also included in the descriptions.

Surface Finishes

The finish for all exposed copper surface features on the circuit must provide surface oxidation and corrosion protection for the land pattern features. The plating’s and coatings studied in this session are evaluated to ensure of their compatibility with both eutectic and lead-free solder alloy compositions. The surface finishes selected for component attachment, after all, is a critical element enabling the most reliable solder interface between land patterns and component terminals.

Wednesday, June 4, 2008:

Routing Strategy

As the IO’s for semiconductor devices become more complex it is a greater challenge to meet all the conditions needed for interconnecting the electronic parts. Lead length, matched conductor pairs and the number of layers required are all at risk in establishing manufacturable advanced electronic product. The discussions will provide some examples of different techniques that can be used in order to improve routing of conductors and the manner in which the circuit performs its functions. The characteristics are based on escape routes from aria array type devices and the number of layers required to achieve a satisfactory solution.

Use of Soldermask

The solder mask is a polymer coating applied after the basic fabrication processes, typically before finish plating. In this session we will have the opportunity to discuss the alternative materials is used to mask off the outer areas of the board where solder is not required and its primary function, to coat, insulate and prevent bridging between attachment features and conductors.

Rigid Boards & HDI

The platform used for mounting electronic components has become more complex and now not only serves as an interconnection function, but also a circuit performance application. The organic materials and the reinforcements used to produce rigid printed boards are reviewed and an analysis is made as to the manner in which this technology can move into the area of what has been defined as High Density Interconnection platforms. It isn’t always as clear as to the benefits that this technology brings to the design team however the industry has standardized significantly on the concepts and a global manufacturing base has evolved to address many of the challenges.

Component Placement

In this session we will detail the SMT Process sequence for component attachment, the methods used for solder paste deposition, automated device placement and reflow solder processing. Also discussed is the current expectation for SMT placement system accuracy, the features required for efficient automated assembly and recommended panelization formats that can improve machine utilization.

Process Control

There was a time when quality was inspected into the product after it was all complete. This methodology has changed over time, and today the industry has adopted process control techniques in order to validate the quality of a product. This concept does not mean that one never looks at the end product; it means rather that when a process has produced the desired defect free product the process is reviewed rather than the product. Some of these principles are described as in-process evaluations, and many manufacturers have used the tools and methods that have been developed in the past ten years to insure their customers that they are meeting all the requirements.

Inspection and Acceptance

• Product quality and the visual acceptability requirements for surface mount assembly will be reviewed with reference to two primary guidance documents; IPC-A-610 and IPC-7095. The IPC-A-610 establishes the attachment criteria for both passive and active surface mount components. The IPC-7095 focuses on the design and assembly implementation of the BGA families of devices and includes defect assessment for voids and other anomolies.

Quality Assesment

If one understands the function of the purchasing agent it also has become more complex with the advent of advanced packaging techniques. The industry has a long history of standardizing the performance and complexity requirements, and these are well documented in the standards written by many organization. What is missing however is that function identified as “State-Of-The Art” where and engineering team is working so close with their manufacturers that the designs are structured to take advantage of the manufacturer’s latest equipment and process characteristics . It is at this poiont that the purchasing agent needs to be part of the team and in many instances most have a good engineering background in order to adequately evaluate the quality being produced.

Future Concepts

In this session, a broad range of system-in-package solutions expressly developed for hand-held wireless and high performance electronic applications will be discussed. We will explore a number of alternative package methodologies that can be considered for system level integration and miniaturization including a combination of chip-scale, multiple-die and new package-on-package innovations.

About the Instructors:
The workshop leader will be Dieter Bergman, Director of Technology Transfer at IPC. Dieter has instructed PCB designers for more than two decades, and was instrumental in the development of the IPC-2221, as well as many other design-related IPC standards.

Vern Solberg is a consultant specializing in surface mount and microelectronic design and assembly. He holds several patents for IC packaging innovations (including the folded-flex 3-D package). He has more than 25 years of experience in design and manufacturing for commercial and aerospace electronic products and is the author of Design Guidelines for Surface Mount and Fine-Pitch Technology, published by McGraw-Hill. He is the chairman of a task group for IPC-7094, Design and Assembly Process Implementation for Flip Chip and Chip Size Packaging.

Location, Times and Hotel Accommodations
The workshop will be held onsite at Tessera Technologies, Inc., 3099 Orchard Drive, San Jose, CA 95134. The course will begin at 8:30 am (with onsite registration and sign-in beginning at 8:00 am) and conclude by 5:00 pm. For out-of-town guests, we recommend that you contact the Sierra Suites Hotel Santa Clara, 3915 Rivermark Plaza, Santa Clara, CA 95054. You may contact the hotel directly at +1 408-486-0800. A special rate has not been contracted.

Registration Information
The registration fees for the workshop are indicated below on the registration form. To register for the any of the workshops, complete the registration form and fax or mail as indicated. For more information, or if the registration deadline has passed, contact the IPC registration department at +1 847-597-2861.

Cancellation Policy: Cancellations must be made one business day prior to the workshop in order to be eligible for a full refund. If the workshop is cancelled, participants will receive a full refund. If you are unable to attend, you may send a co-worker in your place.

Registration Form Early Registration - Register by May 30 , 2008, and save an additional 10% off the prices shown below. Group Discount - Register three individuals from your company at the same time and receive the fourth registration FREE.
Design for Advanced Packaging Workshop Hosted by Tessera, Inc. June 3-4, 2008 - San Jose, Calif. (download the registration form as a pdf here)
Name		Title/Mail Stop
Company
Mailing Address
City/State/ZipCode
Area Code/Phone	Ext.	Fax
E-Mail

IPC/DC member

Nonmember

Design for Advanced Packaging Workshop - Hosted by Tessera, Inc. 06/3-4/2008

$495(U.S.)

$695 (U.S.)

Method of Payment:
Check enclosed in the amount of $________________payable to IPC

P.O. #____________(for IPC members Only) $__________________

Bill my credit card (check one) MasterCard Visa American Express Diners Club

Card Number	Expiration Date
Billing Address
Cardholder	Signature

* Membership status will be verified upon receipt of registration form. Receipts will be sent only upon request.
• Please call if you have a disability requiring accommodations.

Return this form by fax to: +1 847-615-5661,
or mail to: IPC, 3491 Eagle Way
Chicago, IL 60678-1349