IPC introduces a new technical conference including workshops, technical presentations, latest equipment offerings and site visits, all dedicated to the changing world of test and inspection protocols. Different testing methods and strategies will be shared that verify the sum and quality of the parts used in the assembly process (printed boards, electronic components, application-specific subassemblies, etc.).

The risks of partial test and inspection coverage will be examined along with the sampling plan methodologies and how they may be interpreted for the appropriate quality assurance conditions. This conference will give attendees a thorough look at product verification (through testing and inspection) at each level of the manufacturing process.

Attending the Test and Inspection Conference: The Changing World of Test Protocols sponsored by IPC will allow you to examine the methods and practices currently used to validate the performance capability of electronic equipment. And, we will set the stage to explore alternatives, consider cost implications, and incorporate all associated technologies for test and inspection.

Registration Information

Please register by November 30, 2007, to secure your seat at this event. Complete the registration form and fax or mail it to IPC. The technical conference and tabletop displays will be held on December 11, 2007 and in the morning on December 12, 2007. For more information, or if the registration deadline has passed, contact an IPC registration representative at +1 847-597-2861 or send an e-mail to registration@ipc.org.

Cancellation Policy: Cancellations received before December 7, 2007, will be refunded in full. Refunds will not be issued after the start of the program. Individuals failing to cancel will be billed for the registration fee. If the events are cancelled, participants will receive a full refund. If you are unable to attend, you may send a co-worker in your place.

Location and Hotel Accommodation

Both the educational courses and technical conference will take place at the Wyndham San Jose, 1350 North First Street, San Jose, CA. To reserve your room, contact the hotel directly at 408-453-6200 and ask for the IPC conference rate of $139 per night. Rate is subject to change after December 7, 2007.

Design for Testability (DFT) is an engineering discipline that has been successful in reducing test costs and efforts for the past 30+ years.  While it has gained the support of technical people, it has not been widely supported by managers - mainly because they do not want to be bugged down with technical details and engineers have not demonstrated sufficiently the economic benefits resulting from DFT.  Without management understanding and support for DFT, many organizations have not been directed towards DFT and the entire industry has suffered the consequences. To remedy this situation, test professionals have presented panels of discussion at AutoTestCon for the past two years about this issue and are scheduled for sessions at AutoTestCon 2008.  It has been the overwhelming opinion of about a dozen test engineering professional presenters from as many organizations, as well as about 200 people attending the panels, that a group needs to be formed to create DFT guidelines for managers.  Though it is not official, the group can be called the Testability Management Advisory Group (TMAG).

If you are interested in attending this meeting, please contact Louis Ungar at LouisUngar@ieee.org.

A test plan is written, approved and then implemented to fulfill the validation process. Test development activities follow documented procedures. Process have been refined to meet relevant standards of the test development process.

This workshop will give you an overview on each of those test and inspection processes and how to assess proper test protocols strategies within your test and inspection process.

Topics to be Covered

1:00 pm Testability and Inspection Strategies – Louis Ungar, ATE Solutions Inc.

1:45 pm Understanding Electrical Test –Dieter Bergman, IPC

2:30 pm Break

2:45 pm Other Test & Inspection Methodologies – Michaela Brody, Zero Defects

3:30 pm Test Protocol Risk Assessment Strategies – Jack Fisher, Interconnect Technology Analysis, Inc.

Who Will Benefit

Both manufacturing and test engineers from OEM and EMS companies of all sizes will gain a solid understanding of today's test and inspection technologies. The rules have changed and test methodologies have become a collaborative activity between the end customer and the assembler. Cost is a major driver, as well as the need to verify quality and integrity of assemblies in NPI and prototype quantities. Quality Control professionals and Operations management will benefit as these new rules become an integral part of the manufacturing process. Suppliers of inspection and test equipment will contribute as well as benefit from this workshop.

About the Instructors

Dieter Bergman, IPC Director of Technology Transfer, has instructed PCB designers for more than two decades, and was instrumental in the development of the IPC-2221, as well as many other design-related IPC standards.

Louis Ungar president of A.T.E. Solutions, Inc., a leading independent test and testability consulting and educational firm. He has taught ATE and testability courses at UCLA and throughout industry. Ungar is a consultant to The American Society of Test Engineers, has served as Testability Chair for the SMTA and has served on committees for various IEEE standards. Ungar holds a B.S.E.E. and computer science degrees from the University of California at Los Angeles (UCLA) and has completed his course work toward an M.A. in management.

Michaela Brody is one of the co-founders and president of Zero Defects and Z D Test, Inc. She has more than 35 years experience in the PCB industry, including previous management positions with NELCO and Mica Corporation, both laminate manufacturers. She was West Coast Editor for Printed Circuit Fabrication Magazine for 15 years. She has authored numerous technical articles for industry trade publications and was an instructor of technical courses at Irvine Valley College. She has a BA degree in Economics from CSU, Fullerton.

John T. (Jack) Fisher has been in the PCB industry for 35 years, having worked at both IBM and most recently at ITRI (Interconnect Technology Research Institute). While at IBM, Fisher held several senior management and staff positions in maintenance, manufacturing and engineering in both Endicott, N.Y. and Austin, TX. Fisher received IPC’s 1996 Chairman of the Board Award for his work to improve PCB interconnect technology and was elected to IPC's Hall of Fame in 2007. He has authored one book, written numerous papers for trade journals and conferences and is a member of Printed Circuit Design and Manufacture, editorial review board.

We expect a strong turn-out for the tabletop display area during the conference breaks and lunch on December 11,2007 and in the morning on December 12, 2007. Don't miss out on this opportunity to reach your audience. For pricing information and a tabletop application click here(.pdf).

Tabletop Exhibitors

Media Sponsors

Looking for Savings?

• Early Registration - Register by November 5, 2007 and save an additional 10% off of the prices shown below.
• Group Discount - Register three individuals from your company at the same time and receive the fourth
  registration FREE. * Note: The discount will apply to the lowest cost registration.